专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08134568B1 Frame buffer region redirection for multiple graphics adapters 有权
标题翻译：多个图形适配器的帧缓冲区重定向
公开(公告)号：US08134568B1
公开(公告)日：2012-03-13
申请号：US11013078
申请日：2004-12-15
申请人： Rick M. Iwamoto , Franck R. Diard , Brian D. Hutsell
发明人： Rick M. Iwamoto , Franck R. Diard , Brian D. Hutsell
IPC分类号： G06F15/167 , G06F12/10 , G09G5/36
CPC分类号： G06F12/0862 , G06F3/14 , G06F12/1081 , G06F2212/6024 , G09G5/363 , G09G5/39 , G09G5/397 , G09G2360/06
摘要： A system and method for representing multiple prefetchable memory resources, such as frame buffers coupled to graphics devices, as a unified prefetchable memory space for access by a software application. A graphics surface may be processed by multiple graphics devices, with portions of the surface residing in separate frame buffers, each frame buffer coupled to one of the multiple graphics devices. One or more redirection regions may be specified within the unified prefetchable memory space. Accesses within a redirection region are transmitted to a prefetchable memory of a single graphics device. Accesses within the unified prefetchable memory space, but outside of any redirection region may be broadcast to all of the prefetchable memories of the multiple graphics devices.
摘要翻译：用于将多个可预取存储器资源（诸如耦合到图形设备的帧缓冲器）表示为用于由软件应用程序访问的统一的可预取存储器空间的系统和方法。图形表面可以被多个图形装置处理，表面的一部分驻留在单独的帧缓冲器中，每个帧缓冲器耦合到多个图形装置之一。可以在统一的可预取存储器空间内指定一个或多个重定向区域。重定向区域内的访问被传送到单个图形设备的可预取存储器。统一的可预取存储器空间内的任何重定向区域之外的访问可以广播到多个图形设备的所有可预取存储器。

2. 发明授权

US07603503B1 Efficiency based arbiter 有权
标题翻译：基于效率的仲裁者
公开(公告)号：US07603503B1
公开(公告)日：2009-10-13
申请号：US11642791
申请日：2006-12-19
申请人： Brian D. Hutsell , James M. Van Dyke
发明人： Brian D. Hutsell , James M. Van Dyke
IPC分类号： G06F13/18 , G06F13/362
CPC分类号： G06F13/364
摘要： An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.
摘要翻译：仲裁者决定使用效率和/或紧急项来允许从多个客户机访问共享资源（例如存储器）。可以基于从客户端发送到资源的“带内”请求标识，以及客户端缓冲的“带外”请求标识符来确定客户端的紧急度。带外请求标识符和带内请求标识符之间的区别表示请求在客户端缓冲器中的位置。一个小的差异表示请求接近缓冲区的结尾（高紧急度），并且大的差异表示请求远远超过缓冲区（低紧急性）。效率术语包括资源开销的度量，例如在经由共享存储器总线从/从存储器读取/写入数据之间切换所需的时间，或者诸如在DRAM存储体之间切换的时间的银行管理开销。

3. 发明授权

US08271746B1 Tiering of linear clients 有权
标题翻译：线性客户端的分层
公开(公告)号：US08271746B1
公开(公告)日：2012-09-18
申请号：US11612145
申请日：2006-12-18
申请人： Brian D. Hutsell , James M. Van Dyke
发明人： Brian D. Hutsell , James M. Van Dyke
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1642
摘要： Efficient memory management can be performed using a computer system that includes a client which requests access to a memory, a memory interface coupled to the client and to the memory, wherein the memory interface comprises an arbiter to arbitrate requests received from the client to access data stored in the memory, a look ahead structure for managing the memory, a request queue for queuing memory access requests, and wherein the look ahead structure is located before the arbiter so that the look ahead structure communicates with the memory through the arbiter. Efficient memory management can also be performed by sending a memory access request from a client to a look ahead structure and to a request queue, wherein the look ahead structure comprises a row bank direction queue and a tiering logic, checking state of memory being requested using the tiering logic, prioritizing memory requests according to the memory state, selecting a location to be precharged with a precharge arbiter, selecting a location to be activated using an activate arbiter, selecting a location to read or write using a read/write arbiter, and precharging, activating and reading or writing according the selections according to availability of the memory.
摘要翻译：可以使用包括请求访问存储器的客户机，耦合到客户机和存储器的存储器接口的计算机系统来执行高效存储器管理，其中存储器接口包括仲裁器，以仲裁从客户端接收的请求以访问数据存储在存储器中，用于管理存储器的前瞻结构，用于排队存储器访问请求的请求队列，并且其中前瞻结构位于仲裁器之前，使得前瞻性结构通过仲裁器与存储器通信。还可以通过从客户端发送存储器访问请求到前瞻结构和请求队列来执行高效的存储器管理，其中前瞻结构包括行组方向队列和分层逻辑，使用分级逻辑，根据存储器状态对存储器请求进行优先级排序，选择要用预充电仲裁器预先充电的位置，使用激活仲裁器选择要激活的位置，使用读/写仲裁器选择要读取或写入的位置，以及根据存储器的可用性，根据选择预充电，激活和读取或写入。

4. 发明授权

US08700865B1 Compressed data access system and method 有权
标题翻译：压缩数据访问系统和方法
公开(公告)号：US08700865B1
公开(公告)日：2014-04-15
申请号：US11592819
申请日：2006-11-02
申请人： James M. Van Dyke , John H. Edmondson , Lingfeng Yuan , Brian D. Hutsell
发明人： James M. Van Dyke , John H. Edmondson , Lingfeng Yuan , Brian D. Hutsell
IPC分类号： G06F12/00
CPC分类号： G06F12/08 , G06F12/1009 , G06F2212/401
摘要： A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example, a memory stores information and instructions for the engines. The shared resource management unit manages memory operations and handles access requests associated with compressed data.
摘要翻译：描述了共享资源管理系统和方法。在一个实施例中，共享资源管理系统包括多个引擎，共享资源和共享资源管理单元。在一个示例性实现中，共享资源是存储器，共享资源管理单元是存储器管理单元（MMU）。多个发动机执行处理。共享资源支持处理。例如，存储器存储引擎的信息和指令。共享资源管理单元管理存储器操作并处理与压缩数据相关联的访问请求。

5. 发明授权

US08441495B1 Compression tag state interlock 有权
标题翻译：压缩标签状态互锁
公开(公告)号：US08441495B1
公开(公告)日：2013-05-14
申请号：US12649196
申请日：2009-12-29
申请人： James M. Van Dyke , John H. Edmondson , Brian D. Hutsell , Michael F. Harris
发明人： James M. Van Dyke , John H. Edmondson , Brian D. Hutsell , Michael F. Harris
IPC分类号： G09G5/36 , G06T1/60
CPC分类号： G09G5/001 , G09G5/39 , G09G2340/02
摘要： Systems and methods for determining a compression tag state prior to memory client arbitration may reduce the latency for memory accesses. A compression tag is associated with each portion of a surface stored in memory and indicates whether or not the data stored in each portion is compressed or not. A client uses the compression tags to construct memory access requests and the size of each request is based on whether or not the portion of the surface to be accessed is compressed or not. When multiple clients access the same surface the compression tag reads are interlocked with the pending memory access requests to ensure that the compression tags provided to each client are accurate. This mechanism allows for memory bandwidth optimizations including reordering memory access requests for efficient access.
摘要翻译：用于在存储器客户端仲裁之前确定压缩标签状态的系统和方法可以减少存储器访问的延迟。压缩标签与存储在存储器中的表面的每个部分相关联，并指示存储在每个部分中的数据是否被压缩。客户端使用压缩标签来构造存储器访问请求，并且每个请求的大小基于被访问的表面的部分是否被压缩。当多个客户端访问相同的表面时，压缩标签读取与待处理的存储器访问请求互锁，以确保提供给每个客户端的压缩标签是准确的。这种机制允许内存带宽优化，包括重新排序存储器访问请求以进行有效的访问。

6. 发明授权

US07617368B2 Memory interface with independent arbitration of precharge, activate, and read/write 有权
标题翻译：存储器接口，具有预充电，激活和读/写独立仲裁
公开(公告)号：US07617368B2
公开(公告)日：2009-11-10
申请号：US11613120
申请日：2006-12-19
申请人： James M. Van Dyke , Brian D. Hutsell
发明人： James M. Van Dyke , Brian D. Hutsell
IPC分类号： G06F12/00
CPC分类号： G06F13/1647 , G06F13/161
摘要： A memory interface coupling a plurality of clients to a memory having memory banks provides independent arbitration of activate decisions and read/write decisions. In one implementation, precharge decisions are also independently arbitrated.
摘要翻译：将多个客户端耦合到具有存储体的存储器的存储器接口提供激活判定和读/写决定的独立仲裁。在一个实现中，预充电决定也是独立仲裁的。

7. 发明申请

US20070294470A1 MEMORY INTERFACE WITH INDEPENDENT ARBITRATION OF PRECHARGE, ACTIVATE, AND READ/WRITE 有权
标题翻译：具有独立仲裁的存储接口，激活和读/写
公开(公告)号：US20070294470A1
公开(公告)日：2007-12-20
申请号：US11613120
申请日：2006-12-19
申请人： JAMES M. VAN DYKE , Brian D. Hutsell
发明人： JAMES M. VAN DYKE , Brian D. Hutsell
IPC分类号： G06F13/00
CPC分类号： G06F13/1647 , G06F13/161
摘要： A memory interface coupling a plurality of clients to a memory having memory banks provides independent arbitration of activate decisions and read/write decisions. In one implementation, precharge decisions are also independently arbitrated.
摘要翻译：将多个客户端耦合到具有存储体的存储器的存储器接口提供激活判定和读/写决定的独立仲裁。在一个实现中，预充电决定也是独立仲裁的。

8. 发明授权

US07882292B1 Urgency based arbiter 有权
标题翻译：基于紧急程度的仲裁者
公开(公告)号：US07882292B1
公开(公告)日：2011-02-01
申请号：US12551254
申请日：2009-08-31
申请人： James M. Van Dyke , Brian D. Hutsell
发明人： James M. Van Dyke , Brian D. Hutsell
IPC分类号： G06F13/362 , G06F13/36
CPC分类号： G06F13/364
摘要： An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along with the request, and an “out-of-band” request identifier that is buffered by the client. A difference between the out-of-band request identifier and the in-band request identifier indicates the location of the request in the client buffer. A small difference indicates that the request is near the end of the buffer (high urgency), and a large difference indicates that the request is far back in the buffer (low urgency). Efficiency terms include metrics on resource overhead, such as time needed to switch between reading/writing data from/to memory via a shared memory bus, or bank management overhead such as time for switching between DRAM banks.
摘要翻译：仲裁者决定使用效率和/或紧急项来允许从多个客户机访问共享资源（例如存储器）。可以基于从客户端发送到资源的“带内”请求标识，以及客户端缓冲的“带外”请求标识符来确定客户端的紧急度。带外请求标识符和带内请求标识符之间的区别表示请求在客户端缓冲器中的位置。一个小的差异表示请求接近缓冲区的结尾（高紧急度），并且大的差异表示请求远远超过缓冲区（低紧急性）。效率术语包括资源开销的度量，例如在经由共享存储器总线从/从存储器读取/写入数据之间切换所需的时间，或者诸如在DRAM存储体之间切换的时间的银行管理开销。

9. 发明授权

US07680992B1 Read-modify-write memory with low latency for critical requests 有权
标题翻译：对于关键请求，具有低延迟的读 - 修改 - 写入存储器
公开(公告)号：US07680992B1
公开(公告)日：2010-03-16
申请号：US11613142
申请日：2006-12-19
申请人： James M. Van Dyke , Brian D. Hutsell
发明人： James M. Van Dyke , Brian D. Hutsell
IPC分类号： G06F12/08
CPC分类号： G06F12/1425
摘要： A memory interface permits a read-modify-write process to be implemented as an interruptible process. A pending read-modify-write is capable of being temporarily interrupted to service a higher priority memory request.
摘要翻译：存储器接口允许将读 - 修改 - 写入过程实现为可中断过程。待处理的读 - 修改 - 写能力被暂时中断以服务于较高优先级的存储器请求。

10. 发明授权

US07647467B1 Tuning DRAM I/O parameters on the fly 有权
标题翻译：即时调整DRAM I / O参数
公开(公告)号：US07647467B1
公开(公告)日：2010-01-12
申请号：US11642368
申请日：2006-12-19
申请人： Brian D. Hutsell , Sameer M. Gauria , Philip R. Manela , John A. Robinson
发明人： Brian D. Hutsell , Sameer M. Gauria , Philip R. Manela , John A. Robinson
IPC分类号： G06F12/00
CPC分类号： G06F13/4239
摘要： On the fly tuning of parameters used in an interface between a memory (e.g. high speed memory such as DRAM) and a processor requesting access to the memory. In an operational mode, a memory controller couples the processor to the memory. The memory controller can also inhibit the operational mode to initiate a training mode. In the training mode, the memory controller tunes one or more parameters (voltage references, timing skews, etc.) used in an upcoming operational mode. The access to the memory may be from an isochronous process running on a graphics processor. The memory controller determines whether the isochronous process may be inhibited before entering the training mode. If memory buffers for the isochronous process are such that the training mode will not impact the isochronous process, then the memory controller can enter the training mode to tune the interface parameters without negatively impacting the process.
摘要翻译：在用于存储器（例如，诸如DRAM的高速存储器）和请求访问存储器的处理器之间的接口中使用的参数的飞行调谐。在操作模式中，存储器控制器将处理器耦合到存储器。存储器控制器还可以禁止操作模式启动训练模式。在训练模式下，存储器控制器调节在即将到来的操作模式中使用的一个或多个参数（电压参考，时序偏移等）。对存储器的访问可以来自在图形处理器上运行的同步进程。存储器控制器确定在进入训练模式之前是否可以禁止同步过程。如果同步过程的存储器缓冲器使得训练模式不会影响同步过程，则存储器控制器可以进入训练模式以调整接口参数而不会不利地影响该过程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式