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1. 发明申请

US20110057289A1 Ultrashallow Emitter Formation Using ALD and High Temperature Short Time Annealing 有权
标题翻译：使用ALD和高温短时退火的超短发射体形成
公开(公告)号：US20110057289A1
公开(公告)日：2011-03-10
申请号：US12718142
申请日：2010-03-05
申请人： Rick L. Wise , Hiroshi Yasuda
发明人： Rick L. Wise , Hiroshi Yasuda
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/36 , H01L21/02063 , H01L21/2254 , H01L29/66242 , H01L29/66272 , H01L29/73 , H01L29/7325
摘要： An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.
摘要翻译：一种包含双极晶体管的集成电路，其包括具有高于1×1020原子/ cm3的峰值掺杂密度的发射极扩散区域，以及在基极层中小于40纳米深的发射极 - 基极结。一种形成双极晶体管的工艺，其包括在基极层和发射极层之间形成发射极掺杂剂原子层，随后进行闪光或激光退火步骤，以将掺杂剂原子从发射极掺杂剂原子层扩散到基底层中。

2. 发明授权

US08828835B2 Ultrashallow emitter formation using ALD and high temperature short time annealing 有权
标题翻译：使用ALD和高温短时退火的超疏水发射体形成
公开(公告)号：US08828835B2
公开(公告)日：2014-09-09
申请号：US12718142
申请日：2010-03-05
申请人： Rick L. Wise , Hiroshi Yasuda
发明人： Rick L. Wise , Hiroshi Yasuda
IPC分类号： H01L21/331 , H01L21/02 , H01L29/732 , H01L21/225 , H01L29/66
CPC分类号： H01L29/36 , H01L21/02063 , H01L21/2254 , H01L29/66242 , H01L29/66272 , H01L29/73 , H01L29/7325
摘要： An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.
摘要翻译：一种包含双极晶体管的集成电路，其包括具有高于1×1020原子/ cm3的峰值掺杂密度的发射极扩散区域，以及在基极层中小于40纳米深的发射极 - 基极结。一种形成双极晶体管的工艺，其包括在基极层和发射极层之间形成发射极掺杂剂原子层，随后进行闪光或激光退火步骤，以将掺杂剂原子从发射极掺杂剂原子层扩散到基底层中。

3. 发明申请

US20120175710A1 INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS 有权
标题翻译：具有对准（100）NMOS和（110）PMOS FinFET平台通道的集成电路
公开(公告)号：US20120175710A1
公开(公告)日：2012-07-12
申请号：US13425082
申请日：2012-03-20
申请人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
发明人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
IPC分类号： H01L27/092
CPC分类号： H01L27/0886 , G11C11/412 , H01L21/823807 , H01L21/823821 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/045 , Y10S257/90 , Y10S438/973 , Y10S438/982
摘要： An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.
摘要翻译：公开了一种包括多个多栅极FinFET（MuGFET）的集成电路器件。通过在直接硅键合（DSB）混合取向技术（HOT）衬底上的非晶化和晶体再生长形成用于PMOS和NMOS MuGFET的不同晶体取向的晶片。 PMOS MuGFET翅片由具有（110）晶体取向的翅片侧壁表面限定的通道形成。 NMOS MuGFET翅片由曼哈顿布局具有（100）晶体取向的翅片侧壁表面限定的通道形成，其中不同PMOS和NMOS MuGFET的侧壁通道以0°或90°旋转对准。

4. 发明申请

US20100304547A1 REDUCTION OF STI CORNER DEFECTS DURING SPE IN SEMICONDCUTOR DEVICE FABRICATION USING DSB SUBSTRATE AND HOT TECHNOLOGY 审中-公开
标题翻译：使用DSB基板和热技术在半导体器件制造中的SPE期间减少STI拐角缺陷
公开(公告)号：US20100304547A1
公开(公告)日：2010-12-02
申请号：US12637279
申请日：2009-12-14
申请人： Angelo Pinto , Periannan R. Chidambaram , Rick L. Wise
发明人： Angelo Pinto , Periannan R. Chidambaram , Rick L. Wise
IPC分类号： H01L21/76
CPC分类号： H01L21/76275 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045
摘要： A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.
摘要翻译：一种降低混合取向晶体管中的残留STI拐角缺陷的装置和方法，包括：形成直接硅键合衬底，其中具有第二晶体取向的第二硅层以第一晶体取向结合到手柄衬底上，形成衬垫氧化物层在所述第二硅层上，在所述焊盘氧化物层上形成氮化物层，通过所述第二硅层在所述直接硅键合衬底内形成隔离沟槽并进入所述处理衬底，使用光致抗蚀剂构图所述直接硅键合衬底的PMOS区域隔离沟槽的一部分，将直接硅键合衬底的NMOS区域注入和非晶化，去除光致抗蚀剂，进行固相外延，进行再结晶退火，形成STI衬垫，完成前端处理和执行后端处理。

5. 发明申请

US20090057816A1 METHOD TO REDUCE RESIDUAL STI CORNER DEFECTS GENERATED DURING SPE IN THE FABRICATION OF NANO-SCALE CMOS TRANSISTORS USING DSB SUBSTRATE AND HOT TECHNOLOGY 审中-公开
标题翻译：使用DSB基板和热技术在纳米尺寸CMOS晶体管制造中降低SPE期间产生的残留STI角度缺陷的方法
公开(公告)号：US20090057816A1
公开(公告)日：2009-03-05
申请号：US11847053
申请日：2007-08-29
申请人： Angelo Pinto , Periannan R. Chidambaram , Rick L. Wise
发明人： Angelo Pinto , Periannan R. Chidambaram , Rick L. Wise
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L21/76275 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045
摘要： A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.
摘要翻译：一种降低混合取向晶体管中的残留STI拐角缺陷的装置和方法，包括：形成直接硅键合衬底，其中具有第二晶体取向的第二硅层以第一晶体取向结合到手柄衬底上，形成衬垫氧化物层在所述第二硅层上，在所述焊盘氧化物层上形成氮化物层，通过所述第二硅层在所述直接硅键合衬底内形成隔离沟槽并进入所述处理衬底，使用光致抗蚀剂构图所述直接硅键合衬底的PMOS区域隔离沟槽的一部分，将直接硅键合衬底的NMOS区域注入和非晶化，去除光致抗蚀剂，进行固相外延，进行再结晶退火，形成STI衬垫，完成前端处理和执行后端处理。

6. 发明授权

US07160782B2 Method of manufacture for a trench isolation structure having an implanted buffer layer 有权
标题翻译：具有植入缓冲层的沟槽隔离结构的制造方法
公开(公告)号：US07160782B2
公开(公告)日：2007-01-09
申请号：US10870016
申请日：2004-06-17
申请人： Rick L. Wise , Mark S. Rodder
发明人： Rick L. Wise , Mark S. Rodder
IPC分类号： H01L21/762
CPC分类号： H01L21/823878 , H01L21/76237 , H01L29/1054 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.
摘要翻译：本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁中的注入缓冲层（133）。沟槽隔离结构（130）还包括位于注入缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。

7. 发明授权

US06204198B1 Rapid thermal annealing of doped polycrystalline silicon structures formed in a single-wafer cluster tool 有权
标题翻译：在单晶片集成工具中形成的掺杂多晶硅结构的快速热退火
公开(公告)号：US06204198B1
公开(公告)日：2001-03-20
申请号：US09447174
申请日：1999-11-22
申请人： Aditi D. Banerjee , Douglas E. Mercer , Rick L. Wise
发明人： Aditi D. Banerjee , Douglas E. Mercer , Rick L. Wise
IPC分类号： H01L2131
CPC分类号： H01L21/28035
摘要： An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a doped polycrystalline silicon layer insulatively disposed over the semiconductor substrate; and subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds. Preferably, the oxidizing ambient is comprised of: O2,O3, NO, N2O, H2O, and any combination thereof. The temperature is, preferably, around 950 to 1050 C. (more preferably around 1000 C.). The step of subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds, preferably, forms an oxide layer on the polycrystalline silicon layer, which has a thickness which is, preferably, greater than the thickness of a native oxide layer. More preferably, it has a thickness which is greater than 3 nm (more preferably greater than 2 nm). In an alternative embodiment, the thickness of the oxide layer is less than 20 nm (more preferably, less than 10 nm thick).
摘要翻译：本发明的一个实施例是一种在半导体衬底上制造电子器件的方法，该方法包括以下步骤：形成绝缘地设置在半导体衬底上的掺杂多晶硅层; 并在氧化环境中将掺杂的多晶硅层经受约700至1100℃的温度约5至120秒的时间。优选地，氧化环境包括：O 2，O 3，NO，N 2 O，H 2 O及其任何组合。温度优选为950〜1050℃左右（更优选为1000℃左右）。在氧化环境中将掺杂多晶硅层的温度约为700〜1100℃的温度进行约5〜120秒的时间，优选在多晶硅层上形成氧化物层，其厚度为优选地大于天然氧化物层的厚度。更优选地，其厚度大于3nm（更优选大于2nm）。在替代实施例中，氧化物层的厚度小于20nm（更优选小于10nm厚）。

8. 发明授权

US6066893A Contaminant resistant barriers to prevent outgassing 有权
标题翻译：防污屏障防止排气
公开(公告)号：US6066893A
公开(公告)日：2000-05-23
申请号：US159039
申请日：1998-09-23
申请人： Rick L. Wise
发明人： Rick L. Wise
IPC分类号： H01L21/02 , H01L21/8242 , H01L23/00 , H01L23/58 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/1085 , H01L23/564 , H01L27/10852 , H01L28/40 , H01L2924/0002 , Y10S257/913
摘要： An integrated circuit comprises a dielectric layer disposed outwardly from a semiconductor substrate, the dielectric layer comprising at least one cavity having sidewalls extending from an outer surface of the dielectric layer inwardly toward the substrate. The integrated circuit further comprises a contaminant resistant barrier disposed outwardly from at least the sidewalls of the cavity in the dielectric layer.
摘要翻译：集成电路包括从半导体衬底向外设置的电介质层，所述电介质层包括至少一个具有从电介质层的外表面向内延伸到衬底的侧壁的腔。集成电路还包括从电介质层中的空腔的至少侧壁向外设置的抗污染屏障。

9. 发明授权

US6007624A Process for controlling autodoping during epitaxial silicon deposition 失效
标题翻译：在外延硅沉积期间控制自掺杂的工艺
公开(公告)号：US6007624A
公开(公告)日：1999-12-28
申请号：US706364
申请日：1996-08-30
申请人： Rick L. Wise
发明人： Rick L. Wise
IPC分类号： C23C16/52 , H01L21/20 , H01L21/203 , H01L21/205 , H01L21/8249 , H01L27/06 , C30B25/16 , H01L21/31
CPC分类号： H01L21/02532 , H01L21/0245 , H01L21/02617 , Y10S438/902 , Y10S438/906 , Y10S438/916
摘要： A method for controlling the autodoping during epitaxial silicon deposition. First, the substrate (10) is cleaned to remove any native oxide. After being cleaned, the substrate (10) is transferred to the deposition chamber in an inert or vacuum atmosphere to inhibit the growth of a native oxide on the surface of the wafers. A lower temperature (i.e., 500-850.degree. C.) capping layer (14) is deposited to prevent autodoping. Then, the temperature is increased to the desired deposition temperature and the remainder of the epitaxial layer (18) is deposited.
摘要翻译：一种用于在外延硅沉积期间控制自掺杂的方法。首先，清洁基底（10）以去除任何天然氧化物。在清洁之后，将衬底（10）在惰性或真空气氛中转移到沉积室，以抑制晶片表面上的天然氧化物的生长。沉积较低温度（即500-850℃）封盖层（14）以防止自动掺杂。然后，将温度升高至期望的沉积温度，并沉积外延层（18）的其余部分。

10. 发明授权

US5726085A Method of fabricating a dynamic random access memory (DRAM) cell capacitor using hemispherical grain (HSG) polysilicon and selective polysilicon etchback 失效
标题翻译：使用半球形晶粒（HSG）多晶硅和选择性多晶硅回蚀制造动态随机存取存储器（DRAM）单元电容器的方法
公开(公告)号：US5726085A
公开(公告)日：1998-03-10
申请号：US401740
申请日：1995-03-09
申请人： Darius Lammont Crenshaw , Rick L. Wise , Jeffrey McKee
发明人： Darius Lammont Crenshaw , Rick L. Wise , Jeffrey McKee
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90
摘要： A storage node 64 of a capacitor having increased charge storage capacity and a method for forming thereof. A doped polysilicon region 68 is formed. A thin layer of hemispherical grain polysilicon 70 is deposited over the doped polysilicon region 68. The doped polysilicon region 68 and the thin layer of hemispherical grain polysilicon 70 are etched using an etch chemistry that etches the doped polysilicon region 68 faster than the thin layer of hemispherical grain polysilicon 70 to increase the surface area of an upper surface 66 of the storage node 64.
摘要翻译：具有增加的电荷存储容量的电容器的存储节点64及其形成方法。形成掺杂多晶硅区域68。半导体晶粒多晶硅70的薄层沉积在掺杂多晶硅区域68上。掺杂多晶硅区域68和半球状晶粒多晶硅70的薄层被蚀刻使用蚀刻化学品，其蚀刻掺杂多晶硅区域68比薄层半球状晶粒多晶硅70，以增加存储节点64的上表面66的表面积。

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