专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08037285B1 Trace unit 有权
标题翻译：追踪单位
公开(公告)号：US08037285B1
公开(公告)日：2011-10-11
申请号：US11880882
申请日：2007-07-23
申请人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar , Matthew William Ashcraft , Ivan Pavle Radivojevic
发明人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar , Matthew William Ashcraft , Ivan Pavle Radivojevic
IPC分类号： G06F15/00
CPC分类号： G06F12/0875 , G06F9/3017 , G06F9/30189 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/1027 , G06F12/1054 , Y02D10/13
摘要： An instruction processing circuit includes a decoder circuit operable to receive a sequence of instructions and to decode the received sequence of instructions into a first type of sequence of operations, and a trace builder circuit operable to receive at least a portion of the sequence of operations of the first type and to generate, based thereon, a second type of sequence of operations, where the at least a portion of the sequence of operations of the first type represents a first portion of the sequence of instructions, where the first portion of the sequence of instructions includes at most one conditional control transfer instruction that, when present, ends the first portion of the sequence of instructions, and where the sequence of operations of the second type also represents the first portion of the sequence of instructions.
摘要翻译：指令处理电路包括解码器电路，其可操作以接收指令序列并且将接收的指令序列解码为第一类型的操作序列，以及跟踪构建器电路，其可操作以接收至少一部分操作序列第一类型并基于此产生第二类型的操作序列，其中第一类型的操作序列的至少一部分表示指令序列的第一部分，其中序列的第一部分指令包括最多一个条件控制传输指令，当存在时，结束指令序列的第一部分，并且第二类型的操作序列也表示指令序列的第一部分。

2. 发明授权

US08499293B1 Symbolic renaming optimization of a trace 有权
标题翻译：跟踪的符号重命名优化
公开(公告)号：US08499293B1
公开(公告)日：2013-07-30
申请号：US11941912
申请日：2007-11-16
申请人： Matthew William Ashcraft , John Gregory Favor , Christopher Patrick Nelson , Ivan Pavle Radivojevic , Joseph Byron Rowlands , Richard Win Thaik
发明人： Matthew William Ashcraft , John Gregory Favor , Christopher Patrick Nelson , Ivan Pavle Radivojevic , Joseph Byron Rowlands , Richard Win Thaik
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include associating with each register a symbolic expression selected from a set of possible symbolic expressions, locating an operation, if any, that is next within the sequence of operations and setting that operation to be a working operation, where the working operation has associated therewith a destination register and zero or more source registers, and processing the working operation when the working operation and any symbolic expressions of its source registers, if any, match at least one of a set of rules, where each rule specifies that the working operation must match a subset of the operation set, where each rule also specifies that the symbolic expressions, if any, of any source registers of the working operation must match a subset of the possible symbolic expressions, and where the rule also specifies a result, then posting the result as the symbolic expression of the destination register.
摘要翻译：公开了一种用于优化适于由处理器执行的操作序列的方法和装置，以包括将每个寄存器与从一组可能的符号表达式中选择的符号表达式相关联，定位下一个在操作并将操作设置为工作操作，其中工作操作与目标寄存器和零个或多个源寄存器相关联，并且当工作操作和其源寄存器的任何符号表达（如果有的话）匹配时，处理工作操作一组规则中的至少一个，其中每个规则规定工作操作必须与操作集的子集匹配，其中每个规则还规定工作操作的任何源寄存器的符号表达式（如果有的话）必须匹配可能的符号表达式的子集，以及规则还指定结果的位置，然后将结果作为符号表达过程发布目的地寄存器。

3. 发明授权

US07937564B1 Emit vector optimization of a trace 有权
标题翻译：发射矢量优化的痕迹
公开(公告)号：US07937564B1
公开(公告)日：2011-05-03
申请号：US11941908
申请日：2007-11-16
申请人： Matthew William Ashcraft , John Gregory Favor , Christopher Patrick Nelson , Ivan Pavle Radivojevic , Joseph Byron Rowlands , Richard Win Thaik
发明人： Matthew William Ashcraft , John Gregory Favor , Christopher Patrick Nelson , Ivan Pavle Radivojevic , Joseph Byron Rowlands , Richard Win Thaik
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/3808 , G06F9/3838 , G06F9/3853 , G06F11/30
摘要： A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include associating a symbolic expression with each of at least a subset of the registers, holding a set of dependency indications that specify for each particular symbolic expression which, if any, of the other symbolic expressions must be emitted as operations prior to emitting the particular symbolic expression, locating an operation, if any, that is next within the sequence of operations and setting that operation to be a working operation and processing the working operation. Processing is performed by handling the working operation by a combination of updating zero or more of the symbolic expressions and emitting zero or more of the symbolic expressions as operations, identifying which, if any, of the symbolic expressions that were updated in process were updated such that they must be emitted prior to which other, if any, of the symbolic expressions, and then updating the dependency indicators to include any such dependencies, and identifying which, if any, of the symbolic expressions that were updated in process were updated such that they no longer need to be emitted prior to which other, if any, of the symbolic expressions, and then updating the dependency indicators to remove any such dependencies.
摘要翻译：公开了一种用于优化适于由处理器执行的操作序列的方法和装置，以包括将符号表达式与寄存器的至少一个子集中的每一个相关联，保存针对每个特定符号表达式指定的一组依赖性指示，如果有的话，其他符号表达式必须在发出特定符号表达式之前作为操作发出，定位操作序列中的操作（如果有的话），并将该操作设置为工作操作并处理工作操作。处理是通过将更新零个或多个符号表达式并发出零个或多个符号表达式作为操作的组合来处理工作操作来执行的，识别在更新过程中更新的符号表达式中的哪一个更新为它们必须在其他符号表达式之前被发射，然后更新依赖性指示符以包括任何这样的依赖性，并且识别在过程中更新的符号表达式中的哪一个（如果有的话）被更新，使得它们不再需要在其他（如果有的话）符号表达式之前发出，然后更新依赖性指示符以删除任何这样的依赖关系。

4. 发明授权

US07849292B1 Flag optimization of a trace 有权
标题翻译：旗帜优化的痕迹
公开(公告)号：US07849292B1
公开(公告)日：2010-12-07
申请号：US11941900
申请日：2007-11-16
申请人： Matthew William Ashcraft , John Gregory Favor , Christopher Patrick Nelson , Ivan Pavle Radivojevic , Joseph Byron Rowlands , Richard Win Thaik
发明人： Matthew William Ashcraft , John Gregory Favor , Christopher Patrick Nelson , Ivan Pavle Radivojevic , Joseph Byron Rowlands , Richard Win Thaik
IPC分类号： G06F9/00
CPC分类号： G06F9/3853 , G06F8/45 , G06F9/3017 , G06F9/3808 , G06F9/3836
摘要： A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include locating an operation, if any, that is next within the sequence of operations and setting a current operation to be that operation. The current operation is processed as follows: a) de-activating, if not already de-activated, a consumed indicator associated with the current operation; and b) when the current operation is of the producer type, then activating, if not already activated, a producer indicator associated with the current operation, and locating a first set of operations, if any, that i) are earlier in the sequence of operations than the current operation, ii) have their associated producer indicator activated, and iii) have their associated consumed indicator de-activated, and then de-activating the producer indicator associated with each operation in the first set. When the current operation is of the consumer type, then locating a second set of operations, if any, that are earlier in the sequence of operations than the current operation, and then activating, if not already activated, the consumed indicator associated with each operation in the second set.
摘要翻译：公开了一种用于优化适于由处理器执行的操作序列的方法和装置，以包括定位接下来在操作序列内的操作（如果有的话），并将当前操作设置为该操作。当前操作如下处理：a）取消激活与当前操作相关联的消耗的指示符（如果尚未被去激活）以及b）当当前操作是生产者类型时，然后激活（如果尚未激活）与当前操作相关联的生产者指示符，并且定位第一组操作（如果有的话）i）操作，ii）使其相关联的生成器指示符被激活，以及iii）使其相关联的消费指示符被激活，然后去激活与第一组中的每个操作相关联的生成器指示符。当当前操作是消费者类型时，然后找到比当前操作更早的操作序列中的第二组操作（如果有的话），然后激活（如果尚未激活）与每个操作相关联的消耗的指示符在第二集。

5. 发明授权

US07953933B1 Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit 有权
标题翻译：指令缓存，解码电路，基本块高速缓存电路和多块高速缓存电路
公开(公告)号：US07953933B1
公开(公告)日：2011-05-31
申请号：US11880875
申请日：2007-07-23
申请人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
发明人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
IPC分类号： G06F13/00
CPC分类号： G06F9/30061 , G06F9/3802 , G06F9/3808 , G06F9/3836
摘要： An instruction processing circuit includes an instruction cache, a decoder configured to receive at least one of the instructions and to generate, based thereon, a decoder sequence of at least one operation. The circuit includes a basic block cache that includes a basic block sequence of at least one of the operations. The basic block sequence is derived from at least one of the decoder sequences and includes at most one conditional control transfer operation. The circuit includes a multi-block cache that includes a multi-block sequence consisting of at least one of the operations derived from two or more smaller op sequences. A sequencer is configured to generate a prediction for the result of a conditional control transfer operation, select the next sequence of operations, and provide an indication of the next sequence to the instructions cache, the basic block cache, and the multi-block cache.
摘要翻译：指令处理电路包括指令高速缓存器，被配置为接收至少一个指令并且基于此产生至少一个操作的解码器序列的解码器。该电路包括基本块高速缓存，其包括至少一个操作的基本块序列。基本块序列从解码器序列中的至少一个导出，并且至多包括一个条件控制传送操作。该电路包括多块高速缓存，其包括由至少一个从两个或多个较小的操作序列导出的操作中的至少一个的多块序列。定序器被配置为生成条件控制传送操作的结果的预测，选择下一个操作序列，并且向指令高速缓存，基本块高速缓存和多块高速缓存提供下一个序列的指示。

6. 发明授权

US07987342B1 Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer 有权
标题翻译：具有解码器，基本块高速缓存，多块缓存和定序器的跟踪单元
公开(公告)号：US07987342B1
公开(公告)日：2011-07-26
申请号：US11880862
申请日：2007-07-23
申请人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
发明人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30054 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/0875 , G06F12/1027 , G06F12/1054 , Y02D10/13
摘要： An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution circuit of the processor. The instruction processing circuit includes a cache circuit operable to store a second type of sequence of operations that represents at least a portion of a first type of sequence of operations, where the sequence of operations of the second type includes at most one control transfer that, when present, ends a first portion of a sequence of instructions, where the cache circuit is further configured to store a third type of sequence of operations that represents a set of at least two sequences of operations.
摘要翻译：一种用于处理器的指令处理电路，其中所述指令处理电路适于基于一个或多个指令序列向所述处理器的执行电路提供一个或多个操作序列。指令处理电路包括高速缓存电路，其可操作以存储表示第一类型操作序列的至少一部分的第二类型的操作序列，其中第二类型的操作序列包括至多一个控制传输，当存在时，结束指令序列的第一部分，其中高速缓存电路被进一步配置为存储表示至少两个操作序列的集合的第三类操作序列。

7. 发明授权

US07966479B1 Concurrent vs. low power branch prediction 有权
标题翻译：并发与低功率分支预测
公开(公告)号：US07966479B1
公开(公告)日：2011-06-21
申请号：US11880859
申请日：2007-07-23
申请人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
发明人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , G06F9/3017 , G06F9/30189 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/1027 , G06F12/1054
摘要： An instruction processing circuit includes a decoder circuit, a basic block builder circuit, a multi-block builder circuit, first and second predictor circuits, and a sequencer circuit, where the sequencer circuit is operable, in a first environment, to cause the first predictor circuit to generate a prediction for a particular conditional branch op concurrently with the second predictor circuit generating a prediction for another particular conditional branch op, where the sequencer circuit is also operable, in a second environment, to cause the first predictor circuit to generate a prediction for the particular conditional branch op sequentially with the second predictor circuit generating a prediction for the another particular conditional branch operation.
摘要翻译：指令处理电路包括解码器电路，基本块构建器电路，多块构建器电路，第一和第二预测器电路和定序器电路，其中定序器电路在第一环境中可操作以使第一预测器电路，用于与第二预测器电路同时产生用于特定条件分支运算的预测，以产生另一特定条件分支op的预测，其中定序器电路在第二环境中也可操作，以使第一预测电路产生预测对于特定条件分支，顺序地与第二预测器电路产生对另一特定条件分支操作的预测。

8. 发明授权

US07953961B1 Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder 有权
标题翻译：跟踪单元，具有来自解码器（旁路模式）和基本块构建器的操作路径
公开(公告)号：US07953961B1
公开(公告)日：2011-05-31
申请号：US11880863
申请日：2007-07-23
申请人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
发明人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
IPC分类号： G06F9/40
CPC分类号： G06F9/30061 , G06F9/3802 , G06F9/3808 , G06F9/3836
摘要： An instruction processing circuit for a processor includes a decoder circuit, a cache circuit, a sequencer circuit operable to select a next sequence of operations, and an operations fetch circuit operable to convey the next sequence of operations to an execution circuit, receive an indication that a sequencing action of the sequencer circuit is sequencing ahead of the execution circuit, and switch, based on the indication, a source of the operations fetch circuit between the cache circuit and the decoder circuit.
摘要翻译：用于处理器的指令处理电路包括解码器电路，高速缓存电路，可操作以选择下一个操作序列的定序器电路，以及可操作以将下一个操作序列传送到执行电路的操作提取电路，接收指示定序器电路的排序动作在执行电路之前排序，并且基于指示，在高速缓存电路和解码器电路之间切换操作提取电路的源。

9. 发明授权

US07949854B1 Trace unit with a trace builder 有权
标题翻译：跟踪单元与跟踪构建器
公开(公告)号：US07949854B1
公开(公告)日：2011-05-24
申请号：US11880861
申请日：2007-07-23
申请人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
发明人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/0875 , G06F12/1027 , G06F12/1054
摘要： An instruction processing unit includes a trace builder circuit operable to (i) receive at least a portion of a first type of sequence of operations and to generate, based thereon, a second type of sequence of operations, where the portion includes at most one control transfer instruction that, when present, ends the portion, (ii) receive sets of at least two sequences of operations and to generate, based thereon, a plurality of third type of sequences of operations, where a sequence of operations of the third type includes one or more interior control transfer instructions and is generated from the sequence of operations of the second type and another sequence of operations of the third type, and (iii) retrieve the sequence of operations of the second type and the another sequence of operations of the third type from a cache circuit.
摘要翻译：指令处理单元包括跟踪构建器电路，其可操作以（i）接收第一类型的操作序列的至少一部分并且基于此产生第二类型的操作序列，其中该部分至多包括一个控制传送指令，当存在时结束部分，（ii）接收至少两个操作序列的集合，并且基于此生成多个第三类型的操作序列，其中第三类型的操作序列包括一个或多个内部控制传送指令，并且从第二类型的操作序列和第三类型的另一操作序列生成，以及（iii）检索第二类型的操作序列和第二类操作的另一操作序列第三种类型从缓存电路。

10. 发明授权

US07783863B1 Graceful degradation in a trace-based processor 有权
标题翻译：基于跟踪的处理器的平滑降级
公开(公告)号：US07783863B1
公开(公告)日：2010-08-24
申请号：US11923638
申请日：2007-10-24
申请人： Christopher Patrick Nelson , John Gregory Favor , Richard Win Thaik , Matthew William Ashcraft
发明人： Christopher Patrick Nelson , John Gregory Favor , Richard Win Thaik , Matthew William Ashcraft
IPC分类号： G06F9/00
CPC分类号： G06F9/3861 , G06F9/3808 , G06F9/3836 , G06F11/1405
摘要： A method of handling a trace to be aborted includes receiving an indication of a trace to be aborted and an indication of an abort reason corresponding to an execution of the trace to be aborted. The trace to be aborted has a trace type associated therewith and includes a sequence of the operations, and represents a sequence of at least two of the instructions. The method further includes identifying a corrective action based at least in part on the type of the trace to be aborted and on the abort reason, not taking into account a correspondence between the at least one operation that caused the execution to be aborted and the at least one instruction that the at least one operation at least in part represents. A next trace and its trace type is determined for execution, where the determining is based on the trace to be aborted and on the corrective action.
摘要翻译：处理要被中止的迹线的方法包括接收要中止的迹线的指示以及与要中止的迹线的执行相对应的中止原因的指示。要中止的轨迹具有与之相关联的跟踪类型，并且包括操作的序列，并且表示指令中的至少两个的序列。所述方法还包括至少部分地基于要中止的跟踪的类型以及中止原因来识别纠正措施，而不考虑导致执行中止的至少一个操作与在待机中的对应关系所述至少一个操作至少部分地表示的至少一个指令。下一个跟踪及其跟踪类型被确定为执行，其中确定基于要中止的跟踪以及纠正措施。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式