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1. 发明授权

US6009083A Cascade echo canceler arrangement 失效
标题翻译：级联回波消除器布置
公开(公告)号：US6009083A
公开(公告)日：1999-12-28
申请号：US22708
申请日：1998-02-12
申请人： Richard Thomas Flanagan , Jean-Jacques Werner
发明人： Richard Thomas Flanagan , Jean-Jacques Werner
IPC分类号： H04B3/23
CPC分类号： H04B3/23
摘要： The problem of tracking rapid changes in the echo signals associated with modems is eliminated by using an echo canceler consisting of cascaded adaptive filters. Each filter in the structure contributes to the modeling of the overall echo path impulse response, with a longer filter providing the ability to model long echo path impulse responses and a shorter filter providing the ability to track changes in the echo path impulse response over time.
摘要翻译：通过使用由级联自适应滤波器组成的回波消除器来消除跟踪与调制解调器相关联的回波信号的快速变化的问题。该结构中的每个滤波器有助于对整个回波路径脉冲响应的建模，其中较长的滤波器提供对长回波路径脉冲响应建模的能力，以及较短的滤波器，提供跟踪随时间的回波路径脉冲响应变化的能力。

2. 发明授权

US5815496A Cascade echo canceler arrangement 失效
公开(公告)号：US5815496A
公开(公告)日：1998-09-29
申请号：US536905
申请日：1995-09-29
申请人： Richard Thomas Flanagan , Jean-Jacques Werner
发明人： Richard Thomas Flanagan , Jean-Jacques Werner
IPC分类号： H04B3/23
CPC分类号： H04B3/23
摘要： The problem of tracking rapid changes in the echo signals associated with modems is eliminated by using an echo canceler consisting of cascaded adaptive filters. Each filter in the structure contributes to the modeling of the overall echo path impulse response, with a longer filter providing the ability to model long echo path impulse responses and a shorter filter providing the ability to track changes in the echo path impulse response over time.

3. 发明授权

US06693972B1 Data apparatus for maintaining analog line signal during a data sample underrun condition 有权
标题翻译：数据装置，用于在数据样本欠载条件期间维持模拟线路信号
公开(公告)号：US06693972B1
公开(公告)日：2004-02-17
申请号：US09456159
申请日：1999-12-07
申请人： Richard Thomas Flanagan
发明人： Richard Thomas Flanagan
IPC分类号： H04L2704
CPC分类号： H04L27/0002 , H04L25/05
摘要： A data apparatus (e.g., a modem) continues to generate an analog line signal acceptable to a remote data apparatus' receiver when software fails to deliver samples used to generate the line signal to the hardware in time. The data apparatus uses symbols, rather than samples, which are transmitted from a data-pump unit software to an analog front-end (AFE) unit to generate the analog line signal. When the data-pump is late in providing a new set of symbols, the AFE unit uses previous symbols, randomized versions of previous symbols, or some other source of acceptable symbols to generate a transmit line signal. While data errors will still occur, these data errors are a normal occurrence for data apparatus and a link-layer protocol will detect and retransmit the erred data. The invention avoids having the line signal distorted, which can create data transmission outages due to the remote data apparatus entering into a rate change, initiating a retrain operation, or failing entirely.
摘要翻译：数据装置（例如，调制解调器）在软件未能及时向硬件提供用于生成线路信号的采样时，继续产生远程数据装置接收器可接受的模拟线路信号。数据设备使用从数据泵单元软件发送到模拟前端（AFE）单元的符号而不是采样，以产生模拟线路信号。当数据泵在提供新的符号集合时迟到时，AFE单元使用先前的符号，先前符号的随机化版本或可接受的符号的一些其他来源来生成传输线路信号。虽然数据错误仍然会发生，但是这些数据错误是数据设备的正常现象，链路层协议会检测和重传错误的数据。本发明避免了线路信号失真，这可能由于远程数据设备进入速率变化，开始重新训练操作或完全失败而导致数据传输中断。

4. 发明授权

US6163569A Split-architecture modem 有权
标题翻译：分体式调制解调器
公开(公告)号：US6163569A
公开(公告)日：2000-12-19
申请号：US136257
申请日：1998-08-19
申请人： Richard Thomas Flanagan
发明人： Richard Thomas Flanagan
IPC分类号： H04L27/00 , H04B1/38 , H04L5/16
CPC分类号： H04L27/00
摘要： A split-architecture modem splits the physical layer protocol into a logical operations portion and a signal processing portion. A first processor (e.g., a general purpose processor (GPP)) of the modem performs the logical operations of the physical layer protocol along with the data link layer protocol. A second processor (e.g., a digital signal processor (DSP)) of the modem performs the signal processing portion of the physical layer protocol.
摘要翻译：分体式调制解调器将物理层协议分解成逻辑运算部分和信号处理部分。调制解调器的第一处理器（例如，通用处理器（GPP））与数据链路层协议一起执行物理层协议的逻辑操作。调制解调器的第二处理器（例如，数字信号处理器（DSP））执行物理层协议的信号处理部分。

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