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1. 发明授权

US6081849A Method and structure for switching multiple contexts in storage subsystem target device 失效
标题翻译：在存储子系统目标设备中切换多个上下文的方法和结构
公开(公告)号：US6081849A
公开(公告)日：2000-06-27
申请号：US724385
申请日：1996-10-01
申请人： Richard M. Born , Jackson L. Ellis , David M. Springberg , David R. Noeldner , Graeme M. Weston-Lewis
发明人： Richard M. Born , Jackson L. Ellis , David M. Springberg , David R. Noeldner , Graeme M. Weston-Lewis
IPC分类号： G06F3/06 , G06F9/30 , G06F9/40 , G06F13/14
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0674
摘要： A storage target device controller (such as an embedded controller in a SCSI disk drive) processes multiple commands concurrently in accordance with the methods and structures of the present invention. Each command is stored within its own context within the target device controller to retain all unique parameters required for the processing of each command. Processing of multiple commands permits switching of command contexts within the target device to improve utilization of resources associated with the target device. For example, when a first, active, command context is prevented from further processing due to the status of the disk channel, an inactive command context may be swapped with the active command context to better utilize the host channel communication bandwidth. Similarly, a first active command context may be configured to automatically switch to a linked command context upon completion of processing to further ease management of multiple contexts. In a preferred embodiment of the present invention, a set of registers contain the active context while a second set of registers contains an inactive command context. The sets of registers are configured in such a way that the active and inactive context may be rapidly switched with no intervention by the microprocessor. The inactive register set may be read or written directly by the microprocessor, or may be automatically loaded/stored from/to a buffer memory in the target device by shifting a predetermined context structure into the inactive register set through an interface pad with the buffer memory.
摘要翻译：存储目标设备控制器（诸如SCSI盘驱动器中的嵌入式控制器）根据本发明的方法和结构同时处理多个命令。每个命令都存储在目标设备控制器内的自己的上下文中，以保留处理每个命令所需的所有唯一参数。多个命令的处理允许在目标设备内切换命令上下文以提高与目标设备相关联的资源的利用。例如，当由于磁盘信道的状态而阻止第一活动的命令上下文进一步处理时，可以利用活动命令上下文交换不活动命令上下文以更好地利用主机信道通信带宽。类似地，可以配置第一主动命令上下文以在完成处理时自动切换到链接的命令上下文，以进一步简化多个上下文的管理。在本发明的优选实施例中，一组寄存器包含活动上下文，而第二组寄存器包含非活动命令上下文。这些寄存器组被配置成使得无需微处理器干预即可快速切换主动和非活动状态。非活动寄存器组可以由微处理器直接读取或写入，或者可以通过经由具有缓冲存储器的接口板将预定上下文结构移位到非活动寄存器组中而从目标设备中的缓冲存储器中自动加载/存储到缓冲存储器。

2. 发明授权

US6029226A Method and apparatus having automated write data transfer with optional skip by processing two write commands as a single write command 失效
标题翻译：通过将两个写入命令作为单个写入命令来处理具有可选跳过的自动写入数据传送的方法和装置
公开(公告)号：US6029226A
公开(公告)日：2000-02-22
申请号：US724522
申请日：1996-09-30
申请人： Jackson L. Ellis , Richard M. Born , Matthew C. Muresan , Graeme M. Weston-Lewis
发明人： Jackson L. Ellis , Richard M. Born , Matthew C. Muresan , Graeme M. Weston-Lewis
IPC分类号： G06F12/00 , G06F3/06 , G06F9/312 , G06F9/38 , G06F13/00
CPC分类号： G06F9/30043 , G06F3/061 , G06F3/064 , G06F3/0659 , G06F3/0676 , G06F9/3824
摘要： A method and apparatus for writing data to a storage device such as a hard disk drive in which two write commands from an initiator are processed as a single command at the storage device. A first request is received from a small computer systems interface (SCSI) bus to write a first set of data to a storage device. The first set of data is transferred to memory for temporary storage prior to transfer to the storage device. Thereafter, a second write request is received to write a second set of data to the storage device in which the write request includes a logical block address. An ending logical block address determined after transferring the first set of data is compared to the logical block address of the second request to determine whether the second set of data can be written to the storage device along with the first set of data as a single write operation based on the comparison of the logical block address of the second request and the ending logical block address. In response to a determination that the first set of data and the second set of data can be written to the disk as a single write operation, the second set of data is written to the memory as a part of the first write request. The second set of data may be automatically transferred to the memory, to be written to the storage device as a second write operation in response to a determination that the first set of data and the second set of data cannot be written as a single write operation.
摘要翻译：一种用于将数据写入到诸如硬盘驱动器的存储设备的方法和装置，其中来自发起者的两个写入命令作为单个命令被处理在存储设备处。从小型计算机系统接口（SCSI）总线接收第一个请求，以将第一组数据写入存储设备。在传输到存储设备之前，第一组数据被传送到存储器进行临时存储。此后，接收第二写入请求以向存储设备写入第二组数据，其中写请求包括逻辑块地址。将传送第一组数据之后确定的结束逻辑块地址与第二请求的逻辑块地址进行比较，以确定第二组数据是否可以与第一组数据一起写入存储设备作为单个写入基于第二请求的逻辑块地址与结束逻辑块地址的比较的操作。响应于第一组数据和第二组数据可以作为单个写入操作被写入到盘的响应，第二组数据作为第一写入请求的一部分被写入存储器。响应于第一组数据和第二组数据不能被写入作为单个写入操作的确定，第二组数据可以被自动传送到存储器，作为第二写入操作被写入存储设备。

3. 发明授权

US6148326A Method and structure for independent disk and host transfer in a storage subsystem target device 失效
标题翻译：存储子系统目标设备中独立磁盘和主机传输的方法和结构
公开(公告)号：US6148326A
公开(公告)日：2000-11-14
申请号：US719830
申请日：1996-09-30
申请人： Richard M. Born , Jackson L. Ellis , David R. Noeldner
发明人： Richard M. Born , Jackson L. Ellis , David R. Noeldner
IPC分类号： G06F3/06 , G06F9/46 , G06F3/00 , G06F9/00 , G06F13/00
CPC分类号： G06F3/0617 , G06F3/0658 , G06F3/0659 , G06F3/0689 , G06F9/462
摘要： In a storage target device controller capable of managing multiple command contexts, methods and associated apparatus are provided for enabling simultaneous, independent operation of the disk channel and the host channel. In a multi-context target device controller, an active context initiates a requested exchange of data blocks between the host channel and the disk channel of the target device. The controller may swap the active context with an inactive context to better utilize resources of the target device such as the host channel bandwidth. The present invention provides for continued independent operation of the host channel and the disk channel. Counters associated with the active context are only updated by operation of the disk channel if the active context is the initiating context of the disk operations. If an inactive context initiated the disk operations, counters associated with the disk channel retain a count of data blocks exchanged between the buffer memory and the disk channel which are not yet accounted for in the inactive, initiating context. When the inactive, initiating context is again swapped into the active context, the counter associated with the disk channel is used to automatically update the counter in the active context.
摘要翻译：在能够管理多个命令上下文的存储目标设备控制器中，提供了方法和相关联的装置，用于实现磁盘通道和主机通道的同时独立操作。在多上下文目标设备控制器中，活动上下文在目标设备的主机通道和磁盘通道之间发起所请求的数据块交换。控制器可以利用无效上下文来交换活动上下文以更好地利用目标设备的资源，例如主机信道带宽。本发明提供主机通道和磁盘通道的继续独立操作。与活动上下文相关联的计数器只有通过磁盘通道的操作才更新，如果活动上下文是磁盘操作的启动上下文。如果非活动上下文发起磁盘操作，则与磁盘通道相关联的计数器保留缓冲存储器和磁盘通道之间交换的数据块的计数，这些数据块在不活动的启动上下文中尚未被考虑。当非活动的启动上下文再次交换到活动上下文中时，与磁盘通道相关联的计数器被用于在活动上下文中自动更新计数器。

4. 发明授权

US06247040B1 Method and structure for automated switching between multiple contexts in a storage subsystem target device 失效
标题翻译：在存储子系统目标设备中的多个上下文之间进行自动切换的方法和结构
公开(公告)号：US06247040B1
公开(公告)日：2001-06-12
申请号：US08720393
申请日：1996-09-30
申请人： Richard M. Born , Jackson L. Ellis , David R. Noeldner
发明人： Richard M. Born , Jackson L. Ellis , David R. Noeldner
IPC分类号： G06F900
CPC分类号： G06F3/0626 , G06F3/0659 , G06F3/0689
摘要： In a storage target device controller capable of managing multiple command contexts, methods and associated apparatus are provided for automatically managing the plurality of contexts using a state machine model. The state machine model is operable on a target device controller having an active context register set for processing of the presently active transfer on the host channel and an inactive context register set for storing an inactive context. The active context register set and inactive context register set are rapidly and automatically swapped by operation of the state machine model to resume or start processing of an inactive context. Additional inactive contexts are stored in a buffer memory associated with the target device controller. The inactive context register set is automatically stored into a selected one of the additional inactive contexts or loaded from a selected one of the additional inactive contexts by operation of the state machine model of the present invention. The state machine model performs appropriate swap, load, and store operations for contexts in accordance with priorities to improve performance of the target device. The highest priority is an auto-write context corresponding to a write command for which data will be imminently received on the host channel. The next priority is the disk context so as to provide sufficient host channel activity to maintain continuous disk channel operation. The last priority is any other context corresponding to any other command which is neither an auto-write context or the present disk context.
摘要翻译：在能够管理多个命令上下文的存储目标设备控制器中，提供了使用状态机模型来自动管理多个上下文的方法和相关联的装置。状态机模型可在目标设备控制器上操作，所述目标设备控制器具有用于处理主机通道上的当前活动传输的活动上下文寄存器和用于存储非活动上下文的无效上下文寄存器集。活动上下文寄存器组和非活动上下文寄存器集合通过状态机模型的操作快速且自动地交换以恢复或开始处理非活动上下文。附加的无效上下文存储在与目标设备控制器相关联的缓冲存储器中。非活动上下文寄存器集合通过本发明的状态机模型的操作被自动地存储到附加非活动上下文中的所选择的一个中，或从所选择的一个附加非活动上下文中加载。状态机模型根据优先级对上下文执行适当的交换，加载和存储操作，以提高目标设备的性能。最高优先级是对应于在主机通道上将立即接收数据的写入命令的自动写入上下文。下一个优先级是磁盘上下文，以便提供足够的主机通道活动来维持连续的磁盘通道操作。最后一个优先级是对应于既不是自动写入上下文也不是当前磁盘上下文的任何其他命令的任何其他上下文。

5. 发明授权

US06617893B1 Digital variable clock divider 失效
标题翻译：数字可变时钟分频器
公开(公告)号：US06617893B1
公开(公告)日：2003-09-09
申请号：US09052849
申请日：1998-03-31
申请人： Richard M. Born , Jackson L. Ellis
发明人： Richard M. Born , Jackson L. Ellis
IPC分类号： H03K2100
CPC分类号： H03K23/68
摘要： A clock divider circuit and methods of operating same includes a standard integral clock divider circuit and a phase slip non-integral divider circuit for high granularity non-integral clock division. A multi-phase frequency synthesizer produces a plurality of phases of a clock frequency and applies the multiple phases to the divider circuit of the present invention. In a first embodiment, each phase is applied to a phase slip divider circuit which includes a integral divider portion and a programmable phase slip divider portion which receives the output of the integral division portion. Each phase of the input clock may therefore be divided by a wide variety of integral and non-integral divisors. In a second, simpler embodiment, a multi-phase frequency synthesizer produces a plurality of phases and applies the phases to a single phase slip divider. The single phase slip divider of the second embodiment may be configured to stay or shift on each phase of the clock in that consecutive phases may be merged or may remain distinct in the output signal of the phase slip non-integral divider portion of the circuit. The output of the phase slip divider of the second embodiment is then applied to an integral divider portion to produce the final output clock signal. Both embodiments provide for integral and non-integral division of a multi-phase input clock signal. The first embodiment provides for additional flexibility at the expense of added complexity relative to the first embodiment.
摘要翻译：时钟分频器电路及其操作方法包括标准积分时钟分频器电路和用于高粒度非积分时钟分频的相位滑移非积分分频器电路。多相频率合成器产生时钟频率的多个相位，并将多个相位施加到本发明的分频器电路。在第一实施例中，每相被施加到相位分配器电路，该相位分配器电路包括一个整体分配器部分和一个可接收积分分割部分的输出的可编程相位分配器部分。因此，输入时钟的每个相位可以被各种积分和非积分因数除。在第二个更简单的实施例中，多相频率合成器产生多个相位并将相位施加到单相分配器。第二实施例的单相滑动分配器可以被配置为在时钟的每个相位上停留或移动，因为连续相可以被合并或可以在电路的相移非整数分频器部分的输出信号中保持不同。然后将第二实施例的相位分配器的输出施加到积分分配器部分以产生最终输出时钟信号。两个实施例都提供多相输入时钟信号的积分和非积分除法。第一实施例以相对于第一实施例的增加的复杂性为代价提供额外的灵活性。

6. 发明授权

US6131108A Apparatus, and associated method, for generating multi-bit length sequences 失效
标题翻译：用于产生多位长度序列的装置和相关方法
公开(公告)号：US6131108A
公开(公告)日：2000-10-10
申请号：US52890
申请日：1998-03-31
申请人： Richard M. Born , Timothy D. Thompson
发明人： Richard M. Born , Timothy D. Thompson
IPC分类号： G06F7/50 , G06F7/505
CPC分类号： G06F7/505 , G06F2207/3812
摘要： Apparatus, and an associated method, for generating multi-bit sequences used, for instance, to form an address pointer or a data pointer of a computer system. The circuitry is embodied in a single-cycle path and is operable to generate an output sequence which is of a bit length which is a multiple of an input sequence. In one implementation, the circuitry is used to generate 48-bit address pointers and 16-bit data pointers.
摘要翻译：用于生成例如用于形成计算机系统的地址指针或数据指针的多比特序列的装置和相关方法。电路体现在单周期路径中，并且可操作以产生具有作为输入序列的倍数的位长度的输出序列。在一个实现中，电路用于生成48位地址指针和16位数据指针。

7. 发明授权

US6115771A Method and system for converting computer peripheral equipment to SCSI-compliant devices 失效
标题翻译：将计算机外围设备转换为SCSI兼容设备的方法和系统
公开(公告)号：US6115771A
公开(公告)日：2000-09-05
申请号：US52715
申请日：1998-03-31
申请人： Richard M. Born
发明人： Richard M. Born
IPC分类号： G06F13/38 , H04L12/40 , H04L12/64 , G06F13/42
CPC分类号： H04L12/40123 , G06F13/385
摘要： A method and system for converting computer peripheral equipment to SCSI-compliant devices includes an interface controller which converts a mass storage device communicating on an ATA interface to a target device communicating in SCSI commands across an IEEE-1394 interface. The controller converts SCSI commands in CDBs in the IEEE-1394 ORBs to ATA ORBs and then directly to ATA/ATAPI commands, through a mapping function.
摘要翻译：用于将计算机外围设备转换为符合SCSI标准的设备的方法和系统包括接口控制器，其将在ATA接口上通信的大容量存储设备转换为通过IEEE-1394接口以SCSI命令通信的目标设备。控制器通过映射功能将IEEE-1394 ORB中的CDB中的SCSI命令转换为ATA ORB，然后直接转换为ATA / ATAPI命令。

8. 发明授权

US6108812A Target device XOR engine 失效
标题翻译：目标设备XOR引擎
公开(公告)号：US6108812A
公开(公告)日：2000-08-22
申请号：US667204
申请日：1996-06-20
申请人： Richard M. Born
发明人： Richard M. Born
IPC分类号： G06F3/06 , G06F11/10 , G06F11/16 , G06F11/267 , G06F12/16 , G11B20/18 , H03M13/00
CPC分类号： G06F11/1076 , G11B20/1833 , G06F11/10 , G06F11/2215 , G06F2211/1059
摘要： A distributed XOR device that preferably includes a data buffer. The data buffer preferably stores at least two data blocks in an interleaved manner. The data blocks contain data words, and a specific data word for each data block contains CRC bits. In response to certain addresses, the data words of the data blocks are output from the data buffer in an interleaved manner. An XOR engine circuit receives the interleaved data words. The XOR engine circuit preferably includes a data XOR circuit and an error detection circuit. The data XOR circuit preferably performs an exclusive-OR function on pairs of data words, where one data word is from a one data block and the other data word in from the other data block. The generated combinations or results are output to the error detection circuit. The error detection circuit generates CRC bits from the generated combinations or results. Preferably, the CRC bits are encoded with a constant ID.sub.CRC. These encoded CRC bits are compared to the result of the exclusive-OR function on the CRC bits of the data blocks. If these bits are not equal, an error signal is output. The comparison therefore checks whether the XOR engine circuit or the data blocks are in error.
摘要翻译：优选地包括数据缓冲器的分布式异或装置。数据缓冲器优选以交错方式存储至少两个数据块。数据块包含数据字，每个数据块的特定数据字包含CRC位。响应于某些地址，数据块的数据字以交错方式从数据缓冲器输出。 XOR引擎电路接收交织的数据字。 XOR引擎电路优选地包括数据XOR电路和错误检测电路。数据XOR电路优选对数据字对执行异或运算，其中一个数据字来自一个数据块，另一个数据字来自另一个数据块。所生成的组合或结果被输出到错误检测电路。错误检测电路根据所生成的组合或结果生成CRC位。优选地，CRC位用常数IDCRC编码。这些编码的CRC位与数据块的CRC位的异或运算结果进行比较。如果这些位不相等，则输出错误信号。因此，比较检查XOR发动机电路或数据块是否有误。

9. 发明授权

US06631484B1 System for packet communication where received packet is stored either in a FIFO or in buffer storage based on size of received packet 失效
标题翻译：用于分组通信的系统，其中接收的分组基于接收到的分组的大小存储在FIFO或缓冲存储器中
公开(公告)号：US06631484B1
公开(公告)日：2003-10-07
申请号：US09052714
申请日：1998-03-31
申请人： Richard M. Born
发明人： Richard M. Born
IPC分类号： G06F1202
CPC分类号： G06F13/405
摘要： An interface apparatus provides a connection between a host having an IEEE 1394 input/output port and a mass storage device having an ATA input/output port. A receive FIFO and a transmit FIFO within the interface apparatus operates to store small-size packets, or operates to store the buffer address of large-size packets, as the small and large size packets are respectively received from the host or transmitted to the host. In both the host receive and host transmit modes of operation of the interface apparatus, the small-size packets are found in the receive FIFO or the transmit FIFO, whereas the data content of large-size packets is stored in the buffer as the corresponding buffer address is stored in the receive FIFO or the transmit FIFO.
摘要翻译：接口装置提供具有IEEE1394输入/输出端口的主机与具有ATA输入/输出端口的大容量存储设备之间的连接。接口设备中的接收FIFO和发送FIFO操作以存储小尺寸分组，或者操作以存储大尺寸分组的缓冲器地址，因为小型和大型分组分别从主机接收或发送到主机。在接收设备的主机接收和主机发送操作模式中，在接收FIFO或发送FIFO中发现小尺寸分组，而大尺寸分组的数据内容作为相应缓冲器存储在缓冲器中地址存储在接收FIFO或发送FIFO中。

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