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1. 发明授权

US5959308A Epitaxial layer on a heterointerface 失效
标题翻译：异质层上的外延层
公开(公告)号：US5959308A
公开(公告)日：1999-09-28
申请号：US12781
申请日：1993-01-29
申请人： Hisashi Shichijo , Richard J. Matyi
发明人： Hisashi Shichijo , Richard J. Matyi
IPC分类号： H01L21/20 , H01L21/36 , H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072
CPC分类号： H01L21/02381 , H01L21/02463 , H01L21/02507 , H01L21/02546 , H01L21/02658 , Y10S438/933 , Y10S438/938
摘要： Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs (110) on silicon (102) is accomplished by formation of a defect annihilating grid (104) on the silicon (102) prior to the epitaxy of the GaAs (110).
摘要翻译：通过在GaAs（110）的外延生长之前在硅（102）上形成缺陷消除栅（104）来实现晶格失配的半导体材料（例如硅（102）上的GaAs（110））的异质外延。

2. 发明授权

US5238869A Method of forming an epitaxial layer on a heterointerface 失效
标题翻译：在异质界面上形成外延层的方法
公开(公告)号：US5238869A
公开(公告)日：1993-08-24
申请号：US918777
申请日：1992-07-27
申请人： Hisashi Shichijo , Richard J. Matyi
发明人： Hisashi Shichijo , Richard J. Matyi
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02381 , H01L21/02463 , H01L21/02507 , H01L21/02546 , H01L21/02658 , Y10S438/933 , Y10S438/938
摘要： Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs (110) on silicon (102) is accomplished by formation of a defect annihilating grid (104) on the silicon (102) prior to the epitaxy of the GaAs (110).
摘要翻译：晶格失配的半导体材料（例如硅（102）上的GaAs（110））的异质外延通过在GaAs（110）的外延之前在硅（102）上形成缺陷湮灭网格（104）来实现。

3. 发明授权

US4914053A Heteroepitaxial selective-area growth through insulator windows 失效
标题翻译：通过绝缘子窗口进行异质外延选择区域生长
公开(公告)号：US4914053A
公开(公告)日：1990-04-03
申请号：US94231
申请日：1987-09-08
申请人： Richard J. Matyi , Hisashi Shichijo
发明人： Richard J. Matyi , Hisashi Shichijo
IPC分类号： H01L21/20
CPC分类号： H01L21/02381 , H01L21/02463 , H01L21/02546 , H01L21/0262 , H01L21/02639 , Y10S148/026 , Y10S148/048 , Y10S148/072 , Y10S148/154 , Y10S438/933
摘要： Preferred embodiments include growth of GaAs on insulator-masked silicon; the GaAs is single crystal over the silicon but polycrystalline over the insulator. A post=growth anneal extends the single crystal region over the insulator for distances of 2-4 .mu.m.
摘要翻译：优选的实施方案包括在绝缘体掩模的硅上生长GaAs; GaAs是硅上的单晶，而在绝缘体上是多晶的。柱=生长退火将绝缘体上的单晶区延伸到2-4μm的距离。

4. 发明授权

US07250334B2 Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode 有权
标题翻译：金属绝缘体金属（MIM）电容器制造与侧壁间隔和铝帽（ALCAP）顶部电极
公开(公告)号：US07250334B2
公开(公告)日：2007-07-31
申请号：US10909648
申请日：2004-07-31
申请人： Darius L. Crenshaw , Byron L. Williams , Alwin Tsao , Hisashi Shichijo , Satyavolu S. Papa Rao , Kenneth D. Brennan , Steven A. Lytle
发明人： Darius L. Crenshaw , Byron L. Williams , Alwin Tsao , Hisashi Shichijo , Satyavolu S. Papa Rao , Kenneth D. Brennan , Steven A. Lytle
IPC分类号： H01L21/8242
CPC分类号： H01L23/5223 , H01L21/76834 , H01L28/57 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.
摘要翻译：公开了形成MIM（金属绝缘金属）电容器的方法（10），其中即使电容器按比例缩小，也减轻了与铜扩散相关的不利影响。侧壁间隔物（156）抵靠着底部电极/铜扩散阻挡材料层（136）的边缘（137），电容器介电材料层（150）的边缘（151）和至少一些边缘（153）的顶层电极材料层。侧壁间隔物（156）是电介质或非导电的，并且减轻由于铜扩散而在板之间产生的“短路”电流。底部电极扩散阻挡材料（136）减轻了铜扩散和/或铜漂移，从而降低了设备过早失效的可能性。

5. 发明授权

US06392263B1 Integrated structure for reduced leakage and improved fill-factor in CMOS pixel 有权
标题翻译：集成结构，可减少泄漏，改善CMOS像素的填充因子
公开(公告)号：US06392263B1
公开(公告)日：2002-05-21
申请号：US09855251
申请日：2001-05-15
申请人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
发明人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
IPC分类号： H01L2972
CPC分类号： H01L27/14643 , H01L27/14609 , H01L27/1463
摘要： A densely integrated pixel, fabricated by CMOS technology, comprises a photodiode formed by a n-well, with cathode, surrounded by a p-well; a reset MOS transistor formed such that its polysilicon gate is positioned, for diode control, across the junction formed by p-well and n-well regions, and its source is merged with the photodiode cathode; and a sensing MOS transistor formed such that its source is combined with the drain of the reset transistor and its gate is electrically connected to the source of the reset transistor. In the pixel of the invention, the photodiode leakage current is greatly reduced, because no n+/p-well junction is connected to the photodiode, and the fill factor is improved, because the pixel size is much reduced.
摘要翻译：由CMOS技术制造的密集集成的像素包括由n阱形成的光电二极管，阴极由p阱包围; 复位MOS晶体管形成为使得其多晶硅栅极被定位用于二极管控制，跨越由p阱和n阱区域形成的结，并且其源极与光电二极管阴极合并; 以及形成为使得其源极与复位晶体管的漏极组合的感测MOS晶体管，并且其栅极电连接到复位晶体管的源极。在本发明的像素中，光电二极管的漏电流大大降低，因为没有 n + / p-阱结连接到光电二极管，并且填充因子得到改善，因为像素尺寸大大降低。

6. 发明授权

US06303420B1 Integrated bipolar junction transistor for mixed signal circuits 有权
标题翻译：用于混合信号电路的集成双极结型晶体管
公开(公告)号：US06303420B1
公开(公告)日：2001-10-16
申请号：US09618413
申请日：2000-07-18
申请人： Seetharaman Sridhar , Amitava Chatterjee , Hisashi Shichijo , Alec J. Morton
发明人： Seetharaman Sridhar , Amitava Chatterjee , Hisashi Shichijo , Alec J. Morton
IPC分类号： H01L218238
CPC分类号： H01L21/8249
摘要： A method for forming integrated circuit bipolar junction transistors for mixed signal circuits. The implants used to form the well regions of the CMOS circuits 20, 40 form the collector regions of bipolar junction transistors. The CMOS transistor pocket implants form the base region of the bipolar junction transistor, and the CMOS drain extension implants form the emitter region of the bipolar junction transistor.
摘要翻译：一种用于形成用于混合信号电路的集成电路双极结型晶体管的方法。用于形成CMOS电路20,40的阱区域的种植体形成双极结型晶体管的集电极区域。 CMOS晶体管插入口形成双极结型晶体管的基极区域，并且CMOS漏极延伸注入形成双极结型晶体管的发射极区域。

7. 发明申请

US20100197053A1 PROCESS AND TEMPERATURE INSENSITIVE FLICKER NOISE MONITOR CIRCUIT 有权
标题翻译：过程和温度敏感型闪烁噪声监测电路
公开(公告)号：US20100197053A1
公开(公告)日：2010-08-05
申请号：US12761544
申请日：2010-04-16
申请人： Baher S. Haroun , Gaurav Chandra , Vijaya Bhaskar Rentala , Venkatesh Srinivasan , Hisashi Shichijo , Krishnaswamy Nagaraj
发明人： Baher S. Haroun , Gaurav Chandra , Vijaya Bhaskar Rentala , Venkatesh Srinivasan , Hisashi Shichijo , Krishnaswamy Nagaraj
IPC分类号： H01L21/66
CPC分类号： H03M3/35 , H01L22/34 , H03M3/43 , H03M3/438
摘要： In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.
摘要翻译：在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。数字信号以可配置的时间间隔存储以形成数字比特流。将数字比特流与参考进行比较，以确定失败是否在允许的范围内。

8. 发明申请

US20060024899A1 Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode 有权
标题翻译：金属绝缘体金属（MIM）电容器制造与侧壁间隔和铝帽（ALCAP）顶部电极
公开(公告)号：US20060024899A1
公开(公告)日：2006-02-02
申请号：US10909648
申请日：2004-07-31
申请人： Darius Crenshaw , Byron Williams , Alwin Tsao , Hisashi Shichijo , Satyavolu Papa Rao , Kenneth Brennan , Steven Lytle
发明人： Darius Crenshaw , Byron Williams , Alwin Tsao , Hisashi Shichijo , Satyavolu Papa Rao , Kenneth Brennan , Steven Lytle
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L23/5223 , H01L21/76834 , H01L28/57 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.
摘要翻译：公开了形成MIM（金属绝缘金属）电容器的方法（10），其中即使电容器按比例缩小，也减轻了与铜扩散相关的不利影响。侧壁间隔物（156）抵靠着底部电极/铜扩散阻挡材料层（136）的边缘（137），电容器介电材料层（150）的边缘（151）和至少一些边缘（153）的顶层电极材料层。侧壁间隔物（156）是电介质或非导电的，并且减轻由于铜扩散而在板之间产生的“短路”电流。底部电极扩散阻挡材料（136）减轻了铜扩散和/或铜漂移，从而降低了设备过早失效的可能性。

9. 发明授权

US5894145A Multiple substrate bias random access memory device 失效
标题翻译：多重衬底偏置随机存取存储器件
公开(公告)号：US5894145A
公开(公告)日：1999-04-13
申请号：US909904
申请日：1997-08-12
申请人： Ih-Chin Chen , Hisashi Shichijo , Clarence W. Teng
发明人： Ih-Chin Chen , Hisashi Shichijo , Clarence W. Teng
IPC分类号： H01L21/8238 , H01L21/8226 , H01L21/8242 , H01L27/082 , H01L27/092 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10805 , H01L27/105
摘要： A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).
摘要翻译：动态随机存取存储器件（10）包括三个单独的部分 - 输入/输出部分（12），外围晶体管部分（14）和存储器阵列部分（16），全部形成在p型衬底层 18）。动态随机存取存储器件（10）可以为每个部分采用单独的衬底偏置电压。输入/输出部分（12）具有通过n-型阱区域（20）与p-型衬底层（18）隔离的p-型区域（22）。外围晶体管部分（14）具有p型区域（36），其可以通过可选的n型阱区域（40）与p型衬底层（18）隔离，用于那些需要不同衬底偏置的器件外围晶体管部分（14）和存储器阵列部分（16）之间的电压。

10. 发明授权

US5065132A Programmable resistor and an array of the same 失效
标题翻译：可编程电阻和阵列相同
公开(公告)号：US5065132A
公开(公告)日：1991-11-12
申请号：US614473
申请日：1990-11-16
申请人： Albert H. Taddiken , Han-Tzong Yuan , Hisashi Shichijo
发明人： Albert H. Taddiken , Han-Tzong Yuan , Hisashi Shichijo
IPC分类号： G11C11/54 , G06N3/063 , G11C11/34 , G11C16/04 , G11C17/14 , G11C27/00 , H01C13/00 , H01L21/338 , H01L21/822 , H01L27/04 , H01L29/47 , H01L29/78 , H01L29/812 , H01L29/872
CPC分类号： G06N3/0635 , G11C11/34 , G11C16/04 , G11C17/14 , G11C27/00 , H01C13/00 , H01L29/7832 , H01L29/8124
摘要： A programmable resistor 10 is provided having a resistive element 12. Resistive element 12 includes a substrate 26 formed by a layer of semiconductor of a first conductivity-type. A current path 32 is formed in substrate 26 by a layer of semiconductor of a second conductivity-type. An interface 36 having interfacial traps is formed between current path 32 and substrate 26. A backgate 24 is formed adjacent substrate 26. A first switch 14 selectively couples backgate 24 to a first voltage while a second switch 16 selectively couples backgate 24 to a second voltage.
摘要翻译：提供具有电阻元件12的可编程电阻器10.电阻元件12包括由第一导电类型的半导体层形成的衬底26。通过第二导电类型的半导体层在衬底26中形成电流通路32。具有界面陷阱的界面36形成在电流路径32和衬底26之间。背板24形成在衬底26附近。第一开关14选择性地将背栅24耦合到第一电压，而第二开关16选择性地将背栅24耦合到第二电压。

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