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1. 发明授权

US07817466B2 Semiconductor array including a matrix of cells and a method of making a semiconductor array having a matrix of cells 有权
标题翻译：包括单元矩阵的半导体阵列和制造具有单元矩阵的半导体阵列的方法
公开(公告)号：US07817466B2
公开(公告)日：2010-10-19
申请号：US12130918
申请日：2008-05-30
申请人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
发明人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
IPC分类号： G11C11/34
CPC分类号： H01L27/105 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C2211/4016 , H01L21/8232 , H01L21/84 , H01L27/0207 , H01L27/10 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/115 , H01L27/11521 , H01L27/118 , H01L27/11803 , H01L27/12 , H01L27/1203 , H01L29/7841
摘要： A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.
摘要翻译：半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。每个单元耦合到许多控制线，允许选择和读取/写入所述单元。所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

2. 发明申请

US20090086535A1 SEMICONDUCTOR ARRAY 有权
标题翻译：半导体阵列
公开(公告)号：US20090086535A1
公开(公告)日：2009-04-02
申请号：US12130918
申请日：2008-05-30
申请人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
发明人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
IPC分类号： G11C11/34
CPC分类号： H01L27/105 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C2211/4016 , H01L21/8232 , H01L21/84 , H01L27/0207 , H01L27/10 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/115 , H01L27/11521 , H01L27/118 , H01L27/11803 , H01L27/12 , H01L27/1203 , H01L29/7841
摘要： A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.
摘要翻译：半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。每个单元耦合到许多控制线，允许选择和读取/写入所述单元。所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

3. 发明申请

US20060291273A1 Sram memory cell and associated read and write method 有权
标题翻译： Sram内存单元和相关的读写方式
公开(公告)号：US20060291273A1
公开(公告)日：2006-12-28
申请号：US11197737
申请日：2005-08-04
申请人： Franck Genevaux
发明人： Franck Genevaux
IPC分类号： G11C7/02 , G11C11/00
CPC分类号： G11C11/412
摘要： A memory cell comprises a first inverter (IA) and a second inverter (IB) coupled upside down to each other between a first node (A) and a second node (B), and a first access transistor (TA) having a drain coupled to the first node (A), a gate coupled to a word line (WL) and a source coupled to a bit line (BLREAD). The memory cell also comprises a reference transistor (TC) having a drain coupled to the first node (A) and a source coupled to a reference line (BLREF), a cut-off potential (GND) being applied to a gate of the reference transistor (TC). Also disclosed is a memory comprising memory cells as described here above, a write method and an associated read method.
摘要翻译：存储单元包括在第一节点（A）和第二节点（B）之间彼此上下耦合的第一反相器（IA）和第二反相器（IB），以及具有漏极耦合的第一存取晶体管（TA）到第一节点（A），耦合到字线（WL）的栅极和耦合到位线（BLREAD）的源极。存储单元还包括具有耦合到第一节点（A）的漏极和耦合到参考线（BLREF）的源极的参考晶体管（TC），被施加到参考的栅极的截止电位（GND）晶体管（TC）。还公开了包括如上所述的存储器单元，写入方法和相关联的读取方法的存储器。

4. 发明申请

US20050018498A1 Process for controlling the read amplifiers of a memory and corresponding memory integrated circuit 有权
标题翻译：用于控制存储器和相应的存储器集成电路的读取放大器的过程
公开(公告)号：US20050018498A1
公开(公告)日：2005-01-27
申请号：US10880343
申请日：2004-06-29
申请人： Christophe Frey , Franck Genevaux
发明人： Christophe Frey , Franck Genevaux
IPC分类号： G11C7/06 , G11C7/14 , G11C7/00
CPC分类号： G11C7/14 , G11C7/06 , G11C2207/065
摘要： An integrated circuit includes a memory, and the memory includes a memory plane arranged in rows and columns, and a plurality of read amplifiers connected to the columns of the memory plane. A reference path includes first and second reference columns, and a reference memory cell is connected between the first and second reference columns. A reference row is connected to the reference memory cell for selection thereof so that the first reference column conducts a discharge current and the second reference column conducts a leakage current. A control circuit is connected between the first and second reference columns and the read amplifiers. The control circuit provides an activation signal to the read amplifiers when an absolute value of a difference between voltages on the first and second reference columns exceeds a threshold.
摘要翻译：集成电路包括存储器，并且存储器包括以行和列排列的存储器平面以及连接到存储器平面的列的多个读取放大器。参考路径包括第一参考列和第二参考列，并且参考存储单元连接在第一和第二参考列之间。参考行连接到参考存储单元以供选择，使得第一参考列导通放电电流，而第二参考列导通漏电流。控制电路连接在第一和第二参考列和读取放大器之间。当第一和第二参考列上的电压之间的绝对值超过阈值时，控制电路向读取放大器提供激活信号。

5. 发明授权

US07995413B2 Memory device that takes leakage currents into account in activating the read amplifiers 有权
标题翻译：在激活读取放大器时考虑到漏电流的存储器件
公开(公告)号：US07995413B2
公开(公告)日：2011-08-09
申请号：US12061238
申请日：2008-04-02
申请人： Franck Genevaux , Alban Forichon
发明人： Franck Genevaux , Alban Forichon
IPC分类号： G11C7/02
CPC分类号： G11C7/14 , G11C7/08 , G11C11/413
摘要： A memory device is a provided that includes memory cells situated at the intersection of lines and columns, and a dummy path including a first dummy column having two bit lines to which there are connected dummy memory cells, and a circuit adapted to select at least one of the dummy memory cells to discharge one of the dummy bit lines. The dummy path also includes at least one second dummy column adapted to generate a dummy leakage current (representing a leakage current of a column of the memory device selected in read mode), and a circuit adapted to copy the dummy leakage current to the one dummy bit line, so that the discharge of the one dummy bit line also depends on the dummy leakage current.
摘要翻译：提供了一种存储器件，其包括位于行和列的交点处的存储器单元，以及虚拟路径，包括具有连接有虚拟存储器单元的两个位线的第一虚拟列，以及适于选择至少一个的虚拟存储单元以排出虚拟位线。虚拟路径还包括适于产生虚拟泄漏电流（表示在读取模式中选择的存储器件的列的泄漏电流）的至少一个第二虚拟列和适于将虚拟泄露电流复制到一个虚拟的电路位线，使得一个虚拟位线的放电也取决于虚拟泄漏电流。

6. 发明授权

US07623400B2 Memory device with programmable control for activation of read amplifiers 有权
标题翻译：具有可编程控制的存储器件，用于激活读取放大器
公开(公告)号：US07623400B2
公开(公告)日：2009-11-24
申请号：US11824948
申请日：2007-07-03
申请人： Francois Jacquet , Franck Genevaux
发明人： Francois Jacquet , Franck Genevaux
IPC分类号： G11C7/02
CPC分类号： G11C7/14 , G11C7/08
摘要： An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory plane, said dummy path including dummy memory cells connected between two dummy bit lines means of selecting at least one dummy cell designed to discharge at least one of the dummy bit lines, and control means connected to the two dummy bit lines to generate said activation signal, characterized in that said device includes means of programming the number of selected cells to discharge at least said dummy bit line, to adjust the time at which said activation signal is output.
摘要翻译：本发明的实施例涉及包括由位于行和列的交点处的存储器单元组成的存储器平面的存储器件，以及设计成输出信号以激活布置在存储器中的列的底部的读取放大器的虚拟路径所述虚拟路径包括连接在两个虚拟位线之间的虚拟存储器单元，所述虚拟存储单元选择至少一个设计成对所述虚拟位线中的至少一个排放的虚拟单元，以及连接到所述两个虚拟位线的控制单元以产生所述激活信号其特征在于，所述设备包括对所选择的单元的数量进行编程以便至少对所述虚拟位线进行排放的装置，以调整所述激活信号输出的时间。

7. 发明授权

US07280387B2 SRAM cell comprising a reference transistor for neutralizing leakage current and associated read and write method 有权
标题翻译： SRAM单元包括用于中和泄漏电流的参考晶体管以及相关的读和写方法
公开(公告)号：US07280387B2
公开(公告)日：2007-10-09
申请号：US11197737
申请日：2005-08-04
申请人： Franck Genevaux
发明人： Franck Genevaux
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A memory cell comprises a first inverter (IA) and a second inverter (IB) coupled upside down to each other between a first node (A) and a second node (B), and a first access transistor (TA) having a drain coupled to the first node (A), a gate coupled to a word line (WL) and a source coupled to a bit line (BLREAD). The memory cell also comprises a reference transistor (TC) having a drain coupled to the first node (A) and a source coupled to a reference line (BLREF), a cut-off potential (GND) being applied to a gate of the reference transistor (TC). Moreover, an SRAM cell comprising a reference transistor for neutralizing leakage current and associated read and write method is described.
摘要翻译：存储单元包括在第一节点（A）和第二节点（B）之间彼此上下耦合的第一反相器（IA）和第二反相器（IB），以及具有漏极耦合的第一存取晶体管（TA）到第一节点（A），耦合到字线（WL）的栅极和耦合到位线（BLREAD）的源极。存储单元还包括具有耦合到第一节点（A）的漏极和耦合到参考线（BLREF）的源极的参考晶体管（TC），被施加到参考的栅极的截止电位（GND）晶体管（TC）。此外，描述了包括用于中和泄漏电流的参考晶体管和相关联的读和写方法的SRAM单元。

8. 发明申请

US20080008020A1 Memory device with programmable control for activation of read amplifiers 有权
标题翻译：具有可编程控制的存储器件，用于激活读取放大器
公开(公告)号：US20080008020A1
公开(公告)日：2008-01-10
申请号：US11824948
申请日：2007-07-03
申请人： Francois Jacquet , Franck Genevaux
发明人： Francois Jacquet , Franck Genevaux
IPC分类号： G11C11/00 , G11C7/02
CPC分类号： G11C7/14 , G11C7/08
摘要： An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory plane, said dummy path including dummy memory cells connected between two dummy bit lines means of selecting at least one dummy cell designed to discharge at least one of the dummy bit lines, and control means connected to the two dummy bit lines to generate said activation signal, characterised in that said device includes means of programming the number of selected cells to discharge at least said dummy bit line, to adjust the time at which said activation signal is output.
摘要翻译：本发明的实施例涉及包括由位于行和列的交点处的存储器单元组成的存储器平面的存储器件，以及设计成输出信号以激活布置在存储器中的列的底部的读取放大器的虚拟路径所述虚拟路径包括连接在两个虚拟位线之间的虚拟存储器单元，所述虚拟存储单元选择至少一个设计成对所述虚拟位线中的至少一个排放的虚拟单元，以及连接到所述两个虚拟位线的控制单元以产生所述激活信号其特征在于，所述设备包括对所选择的单元的数量进行编程以便至少对所述虚拟位线进行排放的装置，以调整所述激活信号输出的时间。

9. 发明授权

US07057955B2 Dynamically unbalanced sense amplifier 有权
标题翻译：动态不平衡感测放大器
公开(公告)号：US07057955B2
公开(公告)日：2006-06-06
申请号：US10860080
申请日：2004-06-03
申请人： Franck Genevaux , Francois Jacquet
发明人： Franck Genevaux , Francois Jacquet
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C2207/065
摘要： A sense amplifier connected to first and second bit lines, comprising means for precharging said bit lines to a high voltage, means for connecting one or the other of the bit lines to a memory cell, said connection causing according to the state of the memory cell a maintaining of the bit line at the high voltage or a voltage reduction, first and second transistors respectively controlled by the first and second bit lines, and, in series with the first and second transistors, a controllable means for the current through the transistor controlled by the bit line connected to the memory cell to be greater than the current through the other transistor when the voltages of the two bit lines are at the high voltage.
摘要翻译：连接到第一和第二位线的感测放大器包括用于将所述位线预充电到高电压的装置，用于将一个或另一个位线连接到存储器单元的装置，所述连接根据存储器单元的状态分别由第一和第二位线控制的高电压或电压降低的位线的保持，以及与第一和第二晶体管串联的用于通过晶体管控制的电流的可控制装置当两个位线的电压处于高电压时，连接到存储单元的位线大于通过另一个晶体管的电流。

10. 发明授权

US07050348B2 Process for controlling the read amplifiers of a memory and corresponding memory integrated circuit 有权
标题翻译：用于控制存储器和对应的存储器集成电路的读取放大器的过程
公开(公告)号：US07050348B2
公开(公告)日：2006-05-23
申请号：US10880343
申请日：2004-06-29
申请人： Christophe Frey , Franck Genevaux
发明人： Christophe Frey , Franck Genevaux
IPC分类号： G11C7/00
CPC分类号： G11C7/14 , G11C7/06 , G11C2207/065
摘要： An integrated circuit includes a memory, and the memory includes a memory plane arranged in rows and columns, and a plurality of read amplifiers connected to the columns of the memory plane. A reference path includes first and second reference columns, and a reference memory cell is connected between the first and second reference columns. A reference row is connected to the reference memory cell for selection thereof so that the first reference column conducts a discharge current and the second reference column conducts a leakage current. A control circuit is connected between the first and second reference columns and the read amplifiers. The control circuit provides an activation signal to the read amplifiers when an absolute value of a difference between voltages on the first and second reference columns exceeds a threshold.
摘要翻译：集成电路包括存储器，并且存储器包括以行和列排列的存储器平面以及连接到存储器平面的列的多个读取放大器。参考路径包括第一参考列和第二参考列，并且参考存储单元连接在第一和第二参考列之间。参考行连接到参考存储单元以供选择，使得第一参考列导通放电电流，而第二参考列导通漏电流。控制电路连接在第一和第二参考列和读取放大器之间。当第一和第二参考列上的电压之间的绝对值超过阈值时，控制电路向读取放大器提供激活信号。

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