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1. 发明授权

US6141631A Pulse rejection circuit model program and technique in VHDL 失效
标题翻译： VHDL中的脉冲抑制电路模型程序和技术
公开(公告)号：US6141631A
公开(公告)日：2000-10-31
申请号：US47877
申请日：1998-03-25
申请人： Richard D. Blinne , Sudhir K. Patel
发明人： Richard D. Blinne , Sudhir K. Patel
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method determines the behavior of a logic cell that receives input signals resulting in a narrow pulse or "glitch." If the pulse width of the output pulse is narrower than a pulse rejection period, the output pulse is rejected and is not propagated to subsequent logic cells connected to the output. The method employs a first internal logic cell model which is assigned an inertial delay function, and a second internal logic cell model which is assigned a transport delay function. In combination, the first and second logic cell models result in an effective propagation delay value, subject to the pulse rejection feature. An exemplary VHDL model is disclosed. A program product embodies a logic cell model in VHDL providing pulse rejection capabilities for output pulses with pulse width smaller than a pulse rejection period.
摘要翻译：一种方法确定接收输入信号导致窄脉冲或“毛刺”的逻辑单元的行为。如果输出脉冲的脉冲宽度比脉冲抑制周期窄，则输出脉冲被拒绝，不会传播到连接到输出端的后续逻辑单元。该方法采用分配有惯性延迟函数的第一内部逻辑单元模型和被分配有传输延迟函数的第二内部逻辑单元模型。结合起来，第一和第二逻辑单元模型导致有效的传播延迟值，受到脉冲抑制特性的影响。公开了示例性VHDL模型。程序产品体现了VHDL中的逻辑单元模型，为脉冲宽度小于脉冲抑制周期的输出脉冲提供脉冲抑制能力。

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