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1. 发明授权

US06362524B1 Edge seal ring for copper damascene process and method for fabrication thereof 有权
标题翻译：铜镶嵌工艺的边缘密封环及其制造方法
公开(公告)号：US06362524B1
公开(公告)日：2002-03-26
申请号：US09625367
申请日：2000-07-26
申请人： Richard C. Blish , Kurt O. Taylor , David C. Greenlaw
发明人： Richard C. Blish , Kurt O. Taylor , David C. Greenlaw
IPC分类号： H01L2348
CPC分类号： H01L21/7684 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A metal edge seal ring is formed in a trench made up of a large number of short, connected legs in perpendicular relation. Metal is deposited in the trench, and because the metal is comprised of many short segments rather than several long, straight sections, the subsequent chemical-mechanical polishing step does not cause significant cupping of the metal in the trench.
摘要翻译：金属边缘密封环形成在由大量相互垂直的短连接的腿构成的沟槽中。金属沉积在沟槽中，并且由于金属由许多短的段而不是几个长的直的部分组成，所以随后的化学 - 机械抛光步骤不会导致金属在沟槽中的显着的拔罐。

2. 发明授权

US5939766A High quality capacitor for sub-micrometer integrated circuits 失效
标题翻译：用于亚微米集成电路的高品质电容器
公开(公告)号：US5939766A
公开(公告)日：1999-08-17
申请号：US687128
申请日：1996-07-24
申请人： Andre Stolmeijer , David C. Greenlaw
发明人： Andre Stolmeijer , David C. Greenlaw
IPC分类号： H01L23/522 , H01L27/06 , H01L27/04
CPC分类号： H01L27/0688 , H01L23/5223 , H01L2924/0002
摘要： A capacitor is provided for analog applications which can be fabricated with processes conventionally employed to fabricate digital circuitry and which has line spacing that is smaller than interlayer spacing. The capacitor of the present invention is based on intralayer capacitive coupling, rather than interlayer capacitive coupling which is conventionally employed in prior art capacitors. A capacitance can be achieved with the capacitor of the present invention that is higher than can be obtained with conventional capacitors occupying an area on the integrated circuit structure having similar size. Additionally, the capacitor of the present invention can be formed from upper metal layer such as metal-3, metal-4, and metal-5, and when the capacitor is formed from any of the upper metal layers the parasitic capacitance to ground is small.
摘要翻译：提供了用于模拟应用的电容器，其可以通过常规用于制造数字电路的工艺制造，并且具有小于层间距的线间距。本发明的电容器基于层间电容耦合，而不是现有技术电容器中通常采用的层间电容耦合。可以通过本发明的电容器实现电容，该电容高于可占用具有类似尺寸的集成电路结构上的区域的常规电容器所获得的电容。此外，本发明的电容器可以由金属-3，金属-4和金属-5等上金属层形成，并且当电容器由任何上金属层形成时，对地的寄生电容小。

3. 发明授权

US6159851A Borderless vias with CVD barrier layer 有权
标题翻译：具有CVD阻挡层的无边界通孔
公开(公告)号：US6159851A
公开(公告)日：2000-12-12
申请号：US295362
申请日：1999-04-21
申请人： Robert C. Chen , David C. Greenlaw , John A. Iacoponi
发明人： Robert C. Chen , David C. Greenlaw , John A. Iacoponi
IPC分类号： H01L21/285 , H01L21/28 , H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/76862 , H01L21/76843 , H01L21/76852 , H01L21/76877 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Borderless vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an undercut, etched side surface of a lower metal feature. A metal, such as tungsten, is subsequently deposited to fill the borderless via. Embodiments include thermal decomposition of an organic-titanium compound, such as tetrakis-dimethylamino titanium, and treating the deposited titanium nitride in an H.sub.2 /N.sub.2 plasma to lower its resistivity.
摘要翻译：通过最初通过化学气相沉积沉积薄的保形氮化钛层来填充无边界通孔，以覆盖下金属特征的底切蚀刻侧表面。随后沉积诸如钨的金属以填充无边界通孔。实施方案包括有机钛化合物如四 - 二甲基氨基钛的热分解，以及在H 2 / N 2等离子体中处理沉积的氮化钛以降低其电阻率。

4. 发明授权

US6096628A Method of controlling effective channel length of semiconductor device by non-doping implantation at elevated energies 有权
标题翻译：通过在高能量下非掺杂注入来控制半导体器件的有效沟道长度的方法
公开(公告)号：US6096628A
公开(公告)日：2000-08-01
申请号：US187524
申请日：1998-11-06
申请人： David C. Greenlaw , Jan Raebiger
发明人： David C. Greenlaw , Jan Raebiger
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L29/10 , H02L21/425
CPC分类号： H01L29/66575 , H01L21/26506 , H01L21/28518 , H01L29/1033 , H01L21/26513 , H01L29/665 , Y10S148/032
摘要： A semiconductor device and a method of manufacturing a semiconductor device with an effective channel length that is less than the physical gate length avoids requiring improving the masking, lithography and etching process steps by increasing the implantation energy of a pre-amorphizing implant. The pre-amorphizing implant is performed after the doping of the source and drain areas and after activation of the dopants. The implantation energy is sufficient to introduce damage into the substrate to allow for increased movement of the dopants in the substrate. Subsequent annealing steps performed during silicidation cause the source and drain areas to expand toward each other and reduce the effective channel length. This channel length reduction leads to improved device performance through higher I.sub.dsat, etc.
摘要翻译：半导体器件和制造具有小于物理栅极长度的有效沟道长度的半导体器件的方法避免了通过增加预非晶化植入物的注入能量来改善掩模，光刻和蚀刻工艺步骤。在非掺杂的注入之后，在掺杂源极和漏极区域之后以及在激发掺杂剂之后进行。注入能量足以将损伤引入衬底以允许衬底中掺杂剂的增加的移动。在硅化期间执行的后续退火步骤使得源区和漏区相互扩张并减小有效沟道长度。该通道长度减小可以通过更高的Idsat等来改善器件性能。

5. 发明授权

US5989963A Method for obtaining a steep retrograde channel profile 失效
标题翻译：用于获得陡峭的逆行通道轮廓的方法
公开(公告)号：US5989963A
公开(公告)日：1999-11-23
申请号：US897804
申请日：1997-07-21
申请人： Scott D. Luning , David C. Greenlaw , Jonathan Fewkes
发明人： Scott D. Luning , David C. Greenlaw , Jonathan Fewkes
IPC分类号： H01L21/265 , H01L29/10 , H01L21/336
CPC分类号： H01L21/2652 , H01L29/105
摘要： A method of manufacturing a semiconductor device with a steep retrograde profile. The threshold voltage adjust dopant layer and the punchthrough prevent dopant layer are formed in the substrate. All surface capping layers are removed from the active device regions and, the semiconductor device is placed in a chamber and a high vacuum is established after which an inert atmosphere is introduced into the chamber. The anneal to repair the damage to the lattice and to activate the dopant ions in the dopant layers is done in the inert atmosphere with the surface of the substrate maintained clean, that is, free from a capping oxide or other layer formed on the surface of the substrate.
摘要翻译：制造具有陡峭逆行曲线的半导体器件的方法。在衬底中形成阈值电压调整掺杂剂层和穿通防止掺杂剂层。将所有表面覆盖层从有源器件区域中移除，并将半导体器件放置在腔室中，并建立高真空，之后将惰性气体引入腔室。修复对晶格的损伤并激活掺杂剂层中的掺杂剂离子的退火在惰性气氛中进行，其中衬底的表面保持清洁，即，没有形成在表面上的封盖氧化物或其它层底物。

6. 发明授权

US5969425A Borderless vias with CVD barrier layer 失效
公开(公告)号：US5969425A
公开(公告)日：1999-10-19
申请号：US924131
申请日：1997-09-05
申请人： Robert C. Chen , David C. Greenlaw , John A. Iacoponi
发明人： Robert C. Chen , David C. Greenlaw , John A. Iacoponi
IPC分类号： H01L21/285 , H01L21/28 , H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76862 , H01L21/76843 , H01L21/76852 , H01L21/76877 , H01L23/5226 , H01L2924/0002
摘要： Borderless vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an undercut, etched side surface of a lower metal feature. A metal, such as tungsten, is subsequently deposited to fill the borderless via. Embodiments include thermal decomposition of an organic-titanium compound, such as tetrakis-dimethylamino titanium, and treating the deposited titanium nitride in an H.sub.2 /N.sub.2 plasma to lower its resistivity.

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