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1. 发明申请

US20130115227A1 ANTI-ADDL MONOCLONAL ANTIBODY AND USES THEREOF 审中-公开
标题翻译：抗ADDL单克隆抗体及其用途
公开(公告)号：US20130115227A1
公开(公告)日：2013-05-09
申请号：US13809475
申请日：2011-07-13
申请人： Renee C. Gaspar , Paul J. Shughrue , Fubao Wang , Weirong Wang , Ningyan Zhang , Wei-Qin Zhao , Min Xu , Alexander McCampbell
发明人： Renee C. Gaspar , Paul J. Shughrue , Fubao Wang , Weirong Wang , Ningyan Zhang , Wei-Qin Zhao , Min Xu , Alexander McCampbell
IPC分类号： C07K16/18
CPC分类号： C07K16/18 , A61K39/3955 , A61K45/06 , A61K2039/505 , C07K2317/24 , C07K2317/55 , C07K2317/565 , C07K2317/64 , C07K2317/76 , C07K2317/90 , C07K2317/92 , C07K2317/94
摘要： Disclosed are antibodies that bind amyloid beta-derived diffusible ligands, also known as ADDLs. The antibodies are selective for ADDLs, can penetrate the brain, and are useful in methods of detecting ADDLs and diagnosing Alzheimer's disease. The antibodies also block binding of ADDLs to neurons, assembly of ADDLS, and tau phosphorylation and are there useful in methods for the preventing and treating diseases associated with ADDLs.
摘要翻译：公开了结合淀粉样蛋白β-衍生的扩散配体（也称为ADDL）的抗体。抗体对ADDL是有选择性的，可以渗透大脑，并且可用于检测ADDLs和诊断阿尔茨海默氏病的方法。抗体还阻断ADDL与神经元的结合，ADDLS的组装和tau磷酸化，并且在用于预防和治疗与ADDL相关的疾病的方法中是有用的。

2. 外观设计

USD819430S1 Hook 有权
公开(公告)号：USD819430S1
公开(公告)日：2018-06-05
申请号：US29569252
申请日：2016-06-24
申请人： Min Xu
设计人： Min Xu

3. 发明申请

US20160234009A1 Chaotic Baseband Modulation Hopping Based Post-Quantum Physical-Layer Encryption 审中-公开
标题翻译：基于混沌基带调制跳频的后量子物理层加密
公开(公告)号：US20160234009A1
公开(公告)日：2016-08-11
申请号：US14976373
申请日：2015-12-21
申请人： Wenhua Li , Min Xu
发明人： Wenhua Li , Min Xu
IPC分类号： H04L9/00 , H04L29/08
CPC分类号： H04L9/001 , H04L9/0852 , H04L2209/34
摘要： A post-quantum physical-layer encryption/decryption system based on chaotic Baseband Modulation Hopping (BMH). The baseband constellation, mapping, power level, and phase will vary symbol-by-symbol according to assigned random sequences. Pre-shared secret keys are used as the chaotic system parameters, initialization, and quantization parameters to generate the BMH codes. The BMH physical-layer encryption/decryption system can be combined with digital-domain based encryption algorithms such as AES, code-based post-quantum cryptography, and other physical-layer secure communication techniques such as Frequency Hopping (FH) and Direct Sequence Spread Spectrum (DSSS). It can also be combined with Quantum Key Distribution (QKD) to provide mutual authenticated key distribution. This invention can be applied to all kinds of communication systems including wireless (radio frequency, optical, quantum channel, sonar) and wire (optical fiber, power-line, telephone line, wire quantum channel, etc.), single carrier and multi-carrier, OFDM, MIMO channels.
摘要翻译：基于混沌基带调制跳频（BMH）的后量子物理层加密/解密系统。根据分配的随机序列，基带星座，映射，功率电平和相位将逐个符号变化。预共享密钥用作混沌系统参数，初始化和量化参数，以生成BMH码。 BMH物理层加密/解密系统可以与基于数字域的加密算法结合，例如AES，基于代码的后量子密码学和其他物理层安全通信技术，如跳频（FH）和直接序列传播频谱（DSSS）。它也可以与量子密钥分发（QKD）相结合，以提供相互验证的密钥分配。本发明可以应用于无线（射频，光，量子通道，声纳）和线（光纤，电力线，电话线，线量子通道等），单载波和多载波的各种通信系统，载波，OFDM，MIMO信道。

4. 发明授权

US09201832B2 Electronic device with USB interface and method for starting USB communication therefor 有权
标题翻译：具有USB接口的电子设备和用于启动USB通信的方法
公开(公告)号：US09201832B2
公开(公告)日：2015-12-01
申请号：US14113238
申请日：2011-11-21
申请人： Qirui Li , Chao Li , Huiqin Shi , Min Xu , Tao Wang , Pengbin Xu
发明人： Qirui Li , Chao Li , Huiqin Shi , Min Xu , Tao Wang , Pengbin Xu
IPC分类号： H02J1/00 , G06F13/40 , H02J7/00
CPC分类号： G06F13/4068 , H02J7/0052 , H02J2007/0062
摘要： The disclosure provides an electronic device with a Universal Serial Bus (USB) interface and a method for starting USB communication for a USB interface, so as to solve the problem that a mobile phone terminal device can be damaged easily when a charger shares one interface with USB communication in the conventional art. A control pin of the control circuit of the device is connected with a VCHG pin of a power management chip; an output pin of the control circuit is connected with a USB_VBUS pin of a USB interface chip; a power pin of the control circuit is connected with a fixed voltage input end which inputs a high level; and the control circuit is configured to output a fixed voltage from the output pin of the control circuit when detecting that the voltage of the control pin is more than a set threshold and output a low level from the output pin of the control circuit when detecting that the voltage of the control pin is less than the set threshold. The charging voltage (VCHG) of the handheld terminal product is only used as the control signal which is isolated from the voltage output to the USB_VBUS pin, so that the damage to the device is avoided.
摘要翻译：本发明提供一种具有通用串行总线（USB）接口的电子设备和用于启动USB接口的USB通信的方法，以解决当充电器共享一个接口时移动电话终端设备容易损坏的问题传统技术中的USB通信设备的控制电路的控制引脚与电源管理芯片的VCHG引脚连接; 控制电路的输出引脚与USB接口芯片的USB_VBUS引脚连接; 控制电路的电源引脚与输入高电平的固定电压输入端相连; 并且所述控制电路被配置为当检测到所述控制引脚的电压大于设定的阈值时从所述控制电路的输出引脚输出固定电压，并且当检测到所述控制电路的输出引脚时从所述控制电路的输出引脚输出低电平控制引脚的电压小于设定的阈值。手持终端产品的充电电压（VCHG）仅用作与输出到USB_VBUS引脚的电压隔离的控制信号，从而避免了对器件的损坏。

5. 发明授权

US09052967B2 Detecting resource deadlocks in multi-threaded programs by controlling scheduling in replay 有权
标题翻译：通过控制重播中的调度来检测多线程程序中的资源死锁
公开(公告)号：US09052967B2
公开(公告)日：2015-06-09
申请号：US12848023
申请日：2010-07-30
申请人： Qi Gao , Min Xu
发明人： Qi Gao , Min Xu
IPC分类号： G06F9/52 , G06F11/36
CPC分类号： G06F9/524 , G06F11/3636
摘要： A method and system for determining potential deadlock conditions in a target multi-threaded software application. The target application is first run in a virtual machine and the events within the application are recorded. The recorded events are replayed and analyzed to identify potential lock acquisition conflicts occurring between threads of the application. The potential lock acquisition conflicts are identified by analyzing the order in which resource locks are obtained and pairs of resources that have respective locks obtained in different orders are analyzed. These analyzed pairs are used to define a different order of events in the target application that, when the target application is re-run with the second order of events, may trigger a deadlock condition. The target application is then re-run with the different order of events in an attempt to trigger and then identify potential deadlock situations.
摘要翻译：一种用于确定目标多线程软件应用程序中潜在的死锁状况的方法和系统。目标应用程序首先在虚拟机中运行，并记录应用程序中的事件。记录的事件被重放和分析，以识别在应用程序的线程之间发生的潜在锁定获取冲突。通过分析获得资源锁定的顺序来识别潜在锁获取冲突，并分析具有以不同顺序获得的相应锁的资源对。这些分析的对用于定义目标应用程序中不同的事件顺序，当目标应用程序以二次事件重新运行时，可能会触发死锁条件。然后，目标应用程序以不同的事件顺序重新运行，以尝试触发，然后识别潜在的死锁情况。

6. 发明授权

US08823954B2 Low coherence enhanced backscattering tomography and techniques 有权
标题翻译：低相干性增强后向散射层析成像和技术
公开(公告)号：US08823954B2
公开(公告)日：2014-09-02
申请号：US13698360
申请日：2011-05-17
申请人： Min Xu
发明人： Min Xu
IPC分类号： G01B11/14 , G01B9/02 , G01B11/24 , A61B5/00 , G01N21/47
CPC分类号： G01N21/4795 , A61B5/0066 , G01B9/02 , G01B11/14 , G01B11/24 , G01N2021/4709
摘要： A low coherence enhanced backscattering tomography (LEBT) method is disclosed for depth-selective sensing of the superficial layer of tissue. 3D images of the microarchitecture and molecular conformation of the superficial layer of tissue are obtained. The method combines the high resolution advantage of low coherence light and the high sensitivity advantage of light scattering to tissue structure and composition. Intact tissue can be examined without the need of excision or processing. The method can be applied in in situ measurements. According to the method, 3D images of the nuclear morphology and cellular structure for the superficial layer of the tissue are generated; this is particularly useful in detecting cancer and precancer at the earliest stage of carcinogenesis.
摘要翻译：公开了低相干性增强后向散射层析成像（LEBT）方法，用于对组织的表层进行深度选择性感测。获得微结构的3D图像和组织表层的分子构象。该方法结合了低相干光的高分辨率优点和光散射对组织结构和组成的高灵敏度优势。可以检查完整的组织，而不需要切除或加工。该方法可以应用于原位测量。根据该方法，生成组织表层的核形态和细胞结构的3D图像; 这在癌发生的最早阶段检测癌症和癌前期特别有用。

7. 发明申请

US20140059363A1 Electronic device having USB interface and method for starting USB communication with such device 有权
标题翻译：具有USB接口的电子设备和用于启动与这种设备的USB通信的方法
公开(公告)号：US20140059363A1
公开(公告)日：2014-02-27
申请号：US14113947
申请日：2011-11-15
申请人： Yongping Shao , Huiqin Shi , Min Xu , Tao Wang , Tierui Yao , Xiaofeng Zhang
发明人： Yongping Shao , Huiqin Shi , Min Xu , Tao Wang , Tierui Yao , Xiaofeng Zhang
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F13/385 , G06F13/4295 , H02J7/00 , H02J2007/0062
摘要： The present disclosure provides an electronic device having a USB interface and a method for starting USB communication with such an electronic device, so as to solve the problem of a risk of damaging a mobile phone terminal device arising from sharing of an interface by a charger and a USB communication cable in the related art. In the electronic device, a port GPIO of a baseband chip is connected to a pin USB_VBUS of a USB interface of the baseband chip; based on this circuit, a power management chip detects a state of plugging-in-or-pulling-out of the charger and generates a corresponding interrupt request; and the baseband chip controls the GPIO to output a corresponding level according to the interrupt request. By connecting the port GPIO and the pin USB_VBUS and controlling an output level of GPIO with a software, a high level or a low level (as a triggering signal for starting or terminating the USB communication) is input to the pin USB_VBUS, thus avoiding damage to the device.
摘要翻译：本公开提供一种具有USB接口的电子设备和用于开始与这种电子设备的USB通信的方法，以解决由于充电器共享接口而导致的移动电话终端设备损坏的风险的问题，以及相关技术中的USB通信电缆。在电子设备中，基带芯片的端口GPIO连接到基带芯片的USB接口的引脚USB_VBUS; 基于该电路，电源管理芯片检测充电器插拔的状态，并产生相应的中断请求; 并且基带芯片控制GPIO根据中断请求输出相应的电平。通过连接端口GPIO和引脚USB_VBUS并通过软件控制GPIO的输出电平，将高电平或低电平（作为用于启动或终止USB通信的触发信号）输入到引脚USB_VBUS，从而避免损坏到设备。

8. 发明申请

US20120281543A1 Dispatching Method in a CDMA System and Single Mode Chip 有权
标题翻译： CDMA系统和单模芯片中的调度方法
公开(公告)号：US20120281543A1
公开(公告)日：2012-11-08
申请号：US13259628
申请日：2010-07-12
申请人： Zitao Xue , Jian Yang , Min Xu , Cuihong Yang , Chao Li
发明人： Zitao Xue , Jian Yang , Min Xu , Cuihong Yang , Chao Li
IPC分类号： H04W68/02 , H04W24/00
CPC分类号： H04W68/02
摘要： The present invention discloses a scheduling method in a code division multiple access system and single-mode chips, which method comprises the following steps: a single-mode chip of a terminal respectively calculating a paging slot and a paging frequency point of two subscribers with different international mobile subscriber identities of this terminal; doubling the length of a current paging period of each subscriber in the situation that the paging slots are the same and the paging frequency points are different; and scheduling two subscribers to monitor alternately within the extended paging period. The present invention facilitates the achievement of double treats in the CDMA system.
摘要翻译：本发明公开了一种码分多址系统和单模芯片的调度方法，该方法包括以下步骤：分别计算两个用户不同的寻呼时隙的单模芯片和寻呼频点该终端的国际移动用户身份; 在寻呼时隙相同并且寻呼频点不同的情况下，使每个用户的当前寻呼周期的长度加倍; 并调度两个用户在扩展寻呼周期内交替监视。本发明有助于实现CDMA系统中的双重处理。

9. 发明授权

US08289056B2 Phase detector circuit for automatically detecting 270 and 540 degree phase shifts 有权
标题翻译：用于自动检测270度和540度相移的相位检测器电路
公开(公告)号：US08289056B2
公开(公告)日：2012-10-16
申请号：US12327787
申请日：2008-12-03
申请人： Min Xu , Ming-Ju E. Lee
发明人： Min Xu , Ming-Ju E. Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03D13/004 , H03L7/089 , H03L7/0891
摘要： Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating a substantially 270 degree phase shifted clock signal and a substantially 540 degree phase shifted clock signal, a phase detector receiving the system clock signal and the substantially 270 degree phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the substantially 270 degree phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.
摘要翻译：实施例包括实现用于延迟锁定环路（DLL）电路的相位检测器，该电路可操作以检测两个时钟信号之间基本上270度和基本上540度的相位差。在一个实施例中，DLL电路包括延迟线，其接收系统时钟信号并产生基本上270度的相移时钟信号和基本上540度的相移时钟信号，相位检测器接收系统时钟信号和基本270度相位并且被配置为在检测到系统时钟信号和基本上270度的相移时钟信号之间基本上为270度的相移时产生相应的上下信号，耦合到相位检测器的电荷泵，并且被配置为接收上升和下拉信号并响应于此产生控制信号，以及调节器电路，用于从电荷泵接收控制信号，并产生到延迟链的电压控制信号以控制系统时钟信号的延迟。

10. 发明授权

US08102632B2 Electrostatic discharge power clamp trigger circuit using low stress voltage devices 有权
标题翻译：静电放电电源钳位触发电路采用低应力电压器件
公开(公告)号：US08102632B2
公开(公告)日：2012-01-24
申请号：US12406684
申请日：2009-03-18
申请人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
发明人： Yikai Liang , Arvind Bomdica , Samudyatha Suryanarayana , Gayatri Gopalan , Min Xu , Xin Liu , Ming-Ju Edward Lee
IPC分类号： H02H9/00 , H01C7/12 , H02H1/00 , H02H1/04 , H02H3/22 , H02H9/06
CPC分类号： H03K19/00315
摘要： Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.
摘要翻译：描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路，以保护IC免受过多的电源电压和ESD电压的影响。每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。实施例的保护电路包括高电压IO引脚接口，耦合到IO引脚的电压降网络，并且包括串联连接的多个正向偏置二极管以将IO引脚上的高电压降低到低电压电平，耦合在所述电压降网络和接地端子之间的NMOS分流晶体管，以及耦合到所述NMOS分流晶体管的触发电路，以在感测到的输入电压上升时间短于限定的电源电压上升时间时激活所述并联晶体管。

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