专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190102303A1 SOFTWARE-TRANSPARENT HARDWARE PREDICTOR FOR CORE-TO-CORE DATA TRANSFER OPTIMIZATION 审中-公开
公开(公告)号：US20190102303A1
公开(公告)日：2019-04-04
申请号：US15721249
申请日：2017-09-29
申请人： Ren Wang , Joseph Nuzman , Samantika S. Sury , Andrew J. Herdrich , Namakkal N. Venkatesan , Anil Vasudevan , Tsung-Yuan C. Tai , Niall D. McDonnell
发明人： Ren Wang , Joseph Nuzman , Samantika S. Sury , Andrew J. Herdrich , Namakkal N. Venkatesan , Anil Vasudevan , Tsung-Yuan C. Tai , Niall D. McDonnell
IPC分类号： G06F12/0831 , G06F12/084 , G06F12/0811
摘要： Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.

2. 发明申请

US20170192921A1 MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE 审中-公开
公开(公告)号：US20170192921A1
公开(公告)日：2017-07-06
申请号：US14987676
申请日：2016-01-04
申请人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
发明人： Ren Wang , Yipeng Wang , Andrew J. Herdrich , Jr-Shian Tsai , Tsung-Yuan C. Tai , Niall D. McDonnell , Hugh Wilkinson , Bradley A. Burres , Bruce Richardson , Namakkal N. Venkatesan , Debra Bernstein , Edwin Verplanke , Stephen R. Van Doren , An Yan , Andrew Cunningham , David Sonnier , Gage Eads , James T. Clee , Jamison D. Whitesell , Jerry Pirog , Jonathan Kenny , Joseph R. Hasting , Narender Vangati , Stephen Miller , Te K. Ma , William Burroughs
IPC分类号： G06F13/37 , G06F13/16 , G06F12/08
CPC分类号： G06F13/37 , G06F9/3004 , G06F9/46 , G06F12/04 , G06F12/0811 , G06F12/0868 , G06F13/1642 , G06F13/1673 , G06F2212/283 , G06F2212/6046
摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

3. 发明申请

US20210004328A1 HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY FOR INTER-VM COMMUNICATION FOR NFVS AND OTHER PRODUCER-CONSUMER WORKLOADS 有权
公开(公告)号：US20210004328A1
公开(公告)日：2021-01-07
申请号：US17027248
申请日：2020-09-21
申请人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
发明人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
IPC分类号： G06F12/0842 , G06F12/0831 , G06F12/0893 , G06F12/109 , G06F12/0813 , G06F9/455
摘要： Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

4. 发明申请

US20160182373A1 TECHNOLOGIES FOR NETWORK DEVICE FLOW LOOKUP MANAGEMENT 审中-公开
标题翻译：网络流量查询管理技术
公开(公告)号：US20160182373A1
公开(公告)日：2016-06-23
申请号：US14580801
申请日：2014-12-23
申请人： Ren Wang , Namakkal N. Venkatesan , Aamer Jaleel , Tsung-Yuan C. Tai , Sameh Gobriel , Christian Maciocco
发明人： Ren Wang , Namakkal N. Venkatesan , Aamer Jaleel , Tsung-Yuan C. Tai , Sameh Gobriel , Christian Maciocco
IPC分类号： H04L12/743 , H04L12/747 , H04L29/06
CPC分类号： H04L45/7453 , H04L45/742 , H04L69/22
摘要： Technologies for managing network flow lookups of a network device include a network controller and a target device, each communicatively coupled to the network device. The network device includes a cache for a processor of the network device and a main memory. The network device additionally includes a multi-level hash table having a first-level hash table stored in the cache of the network device and a second-level hash table stored in the main memory of the network device. The network device is configured to determine whether to store a network flow hash corresponding to a network flow indicating the target device in the first-level or second-level hash table based on a priority of the network flow provided to the network device by the network controller.
摘要翻译：用于管理网络设备的网络流查找的技术包括网络控制器和目标设备，每个通信地耦合到网络设备。网络设备包括用于网络设备的处理器的缓存和主存储器。网络设备还包括具有存储在网络设备的高速缓存中的第一级散列表的多级散列表和存储在网络设备的主存储器中的第二级散列表。网络设备被配置为基于由网络提供给网络设备的网络流的优先级来确定是否将与指示目标设备的网络流相对应的网络流哈希存储在第一级或第二级哈希表中控制器。

5. 发明申请

US20160182351A1 TECHNOLOGIES FOR NETWORK PACKET CACHE MANAGEMENT 有权
标题翻译：网络包高速缓存管理技术
公开(公告)号：US20160182351A1
公开(公告)日：2016-06-23
申请号：US14580792
申请日：2014-12-23
申请人： Ren Wang , Sameh Gobriel , Christian Maciocco , Tsung-Yuan C. Tai , Ben-Zion Friedman , Hang T. Nguyen , Namakkal N. Venkatesan , Michael A. O'Hanlon , Shrikant M. Shah , Sanjeev Jain
发明人： Ren Wang , Sameh Gobriel , Christian Maciocco , Tsung-Yuan C. Tai , Ben-Zion Friedman , Hang T. Nguyen , Namakkal N. Venkatesan , Michael A. O'Hanlon , Shrikant M. Shah , Sanjeev Jain
IPC分类号： H04L12/757 , H04L12/721 , H04L12/727
CPC分类号： H04L67/2852 , H04L41/0893 , H04L45/38 , H04L45/745 , H04L45/7453 , H04L49/00
摘要： Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.
摘要翻译：用于识别网络分组的高速缓存行的技术，用于从通信地耦合到网络控制器的网络设备的处理器上的缓存驱逐。网络设备被配置为基于在处理网络分组之后不需要网络分组的确定来确定与网络分组相对应的高速缓存行是否要从高速缓存中逐出，并提供指示基于从网络控制器接收到的逐出策略，缓存行将从缓存中逐出。

6. 发明申请

US20170163575A1 MECHANISM TO SUPPORT MULTIPLE-WRITER/MULTIPLE-READER CONCURRENCY FOR SOFTWARE FLOW/PACKET CLASSIFICATION ON GENERAL PURPOSE MULTI-CORE SYSTEMS 审中-公开
公开(公告)号：US20170163575A1
公开(公告)日：2017-06-08
申请号：US14960993
申请日：2015-12-07
申请人： Ren Wang , Christian Maciocco , Namakkal N. Venkatesan , Tsung-Yuan C. Tai
发明人： Ren Wang , Christian Maciocco , Namakkal N. Venkatesan , Tsung-Yuan C. Tai
IPC分类号： H04L12/861 , H04L12/743 , H04L12/741 , H04L12/721
CPC分类号： H04L49/9094 , H04L45/38 , H04L45/54 , H04L45/7453
摘要： Methods and apparatus to support multiple-writer/multiple-reader concurrency for software flow/packet classification on general purpose multi-core systems. A flow table with rows mapped to respective hash buckets with multiple entry slots is implemented in memory of a host platform with multiple cores, with each bucket being associated with a version counter. Multiple writer and reader threads are run on the cores, with writers providing updates to the flow table data. In connection with inserting new key data, a determination is made to which buckets will be changed, and access rights to those buckets are acquired prior to making any changes. For example, under a flow table employing cuckoo hashing, access rights are acquired to buckets along a full cuckoo path. Once the access rights are obtained, a writer is enabled to update data in the applicable buckets to effect entry of the new key data, while other writer threads are prevented from changing any of these buckets, but may concurrently insert or modify key data in other buckets.

7. 发明授权

US10218647B2 Mechanism to support multiple-writer/multiple-reader concurrency for software flow/packet classification on general purpose multi-core systems 有权
公开(公告)号：US10218647B2
公开(公告)日：2019-02-26
申请号：US14960993
申请日：2015-12-07
申请人： Ren Wang , Christian Maciocco , Namakkal N. Venkatesan , Tsung-Yuan C. Tai
发明人： Ren Wang , Christian Maciocco , Namakkal N. Venkatesan , Tsung-Yuan C. Tai
IPC分类号： H04L12/861 , H04L12/721 , H04L12/743 , H04L12/741
摘要： Methods and apparatus to support multiple-writer/multiple-reader concurrency for software flow/packet classification on general purpose multi-core systems. A flow table with rows mapped to respective hash buckets with multiple entry slots is implemented in memory of a host platform with multiple cores, with each bucket being associated with a version counter. Multiple writer and reader threads are run on the cores, with writers providing updates to the flow table data. In connection with inserting new key data, a determination is made to which buckets will be changed, and access rights to those buckets are acquired prior to making any changes. For example, under a flow table employing cuckoo hashing, access rights are acquired to buckets along a full cuckoo path. Once the access rights are obtained, a writer is enabled to update data in the applicable buckets to effect entry of the new key data, while other writer threads are prevented from changing any of these buckets, but may concurrently insert or modify key data in other buckets.

8. 发明申请

US20180095880A1 PROCESSORS AND METHODS FOR MANAGING CACHE TIERING WITH GATHER-SCATTER VECTOR SEMANTICS 审中-公开
公开(公告)号：US20180095880A1
公开(公告)日：2018-04-05
申请号：US15282483
申请日：2016-09-30
申请人： Kshitij A. Doshi , Namakkal N. Venkatesan , Ren Wang , Andrew J. Herdrich
发明人： Kshitij A. Doshi , Namakkal N. Venkatesan , Ren Wang , Andrew J. Herdrich
IPC分类号： G06F12/0811 , G06F9/30
CPC分类号： G06F12/0811 , G06F9/3004 , G06F12/128 , G06F2212/283 , Y02D10/13
摘要： Processors and methods implementing a machine instruction to perform cache line demotion on multiple cache lines to enable efficient sharing of cache lines between processor cores. One general aspect includes a processor comprising: a plurality of hardware processor cores, where each of the hardware processor cores to include a first cache. The processor also includes a second cache, communicatively coupled to and shared by the plurality of hardware processor cores. The processor to support a first machine instruction, the first machine instruction to include a vector register operand identifying a vector register which contains a plurality of data elements each used to identify a cache line. An execution of the first machine instruction by one of the plurality of hardware processor cores to cause a plurality of identified cache lines to be demoted, such that the demoted cache lines are moved from the first cache to the second cache.

9. 发明申请

US20190102312A1 LAZY INCREMENT FOR HIGH FREQUENCY COUNTERS 审中-公开
公开(公告)号：US20190102312A1
公开(公告)日：2019-04-04
申请号：US15721800
申请日：2017-09-30
申请人： Niall D. McDonnell , Christopher MacNamara , John J. Browne , Andrew Cunningham , Brendan Ryan , Patrick Fleming , Namakkal N. Venkatesan , Bruce Richardson , Tomasz Kantecki , Sean Harte , Pierre Laurent
发明人： Niall D. McDonnell , Christopher MacNamara , John J. Browne , Andrew Cunningham , Brendan Ryan , Patrick Fleming , Namakkal N. Venkatesan , Bruce Richardson , Tomasz Kantecki , Sean Harte , Pierre Laurent
IPC分类号： G06F12/0888 , G06F12/0806 , G06F12/0837 , G06F12/0817
摘要： A computing apparatus, including: a processor; a pointer to a counter memory location; and a lazy increment counter engine to: receive a stimulus to update the counter; and lazy increment the counter including issuing a weakly-ordered increment directive to the pointer.

10. 发明申请

US20150341473A1 PACKET FLOW CLASSIFICATION 有权
标题翻译：分组流程分类
公开(公告)号：US20150341473A1
公开(公告)日：2015-11-26
申请号：US14286975
申请日：2014-05-23
申请人： Cristian Florin F. Dumitrescu , Namakkal N. Venkatesan , Pierre Laurent , Bruce Richardson
发明人： Cristian Florin F. Dumitrescu , Namakkal N. Venkatesan , Pierre Laurent , Bruce Richardson
IPC分类号： H04L29/06 , H04L12/743
CPC分类号： H04L69/22 , H04L12/6418 , H04L45/7453
摘要： Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key. The computing device handles processing of received data packets such that a fetch classification operation is performed by the flow classification module on the first received data packet while a non-fetch classification operation is performed by the flow classification module on a second received data packet.
摘要翻译：在计算设备上进行数据包流分类的技术包括包括多个散列表桶的散列表，其中每个散列表桶将多个密钥映射到对应的业务流。计算设备对接收到的数据分组执行分组流分类，其中分组流分类包括多个顺序分类阶段，并且在每个分类阶段执行获取分类操作和非获取分类操作。获取分类操作包括：基于第一接收数据分组的一组分组字段来预取第一接收数据分组的密钥以便在随后的分类阶段期间使用，以便基于密钥签名从散列表预取哈希表桶的预取密钥用于另一后续分类阶段，并且基于预取的散列表桶和预取密钥预取要应用于第一接收数据分组的业务流。所述计算装置处理所接收的数据分组的处理，使得由所述流分类模块对所述第一接收数据分组执行取样分类操作，同时由所述流分类模块对第二接收数据分组进行非取指分类操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式