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1. 发明申请

US20080052494A1 Method And Device For Operand Processing In A Processing Unit 审中-公开
标题翻译：处理单元中操作数处理的方法和装置
公开(公告)号：US20080052494A1
公开(公告)日：2008-02-28
申请号：US10577022
申请日：2004-08-07
申请人： Reinhard Weiberle , Thomas Kottke , Andreas Steininger
发明人： Reinhard Weiberle , Thomas Kottke , Andreas Steininger
IPC分类号： G06F15/76
CPC分类号： G06F9/30181 , G06F9/30189 , G06F9/383 , G06F9/3851 , G06F9/3869 , G06F9/3885 , G06F11/1641 , G06F2201/845
摘要： A method and a device for operand processing in a processing unit having at least two execution units, which are able to be operated at a predefinable clock cycle. The execution units are controlled by control signals for the processing of the operands and a switch is possible between a first operating mode and a second operating mode. In the first operating mode, both execution units are supplied with the same operands, and in the second operating mode different operands are supplied to both execution units, and both execution units are controlled by the same control signals for the processing of the operands in the first operating mode, and both execution units are controlled by different control signals for the processing of the operands in the second operating mode.
摘要翻译：一种用于具有至少两个执行单元的处理单元中的操作数处理的方法和装置，其能够以可预定的时钟周期操作。执行单元由用于处理操作数的控制信号控制，并且可以在第一操作模式和第二操作模式之间切换。在第一操作模式中，两个执行单元被提供相同的操作数，并且在第二操作模式中，将不同的操作数提供给两个执行单元，并且两个执行单元由相同的控制信号控制，用于处理第一操作模式，并且两个执行单元由不同的控制信号控制，用于处理第二操作模式中的操作数。

2. 发明申请

US20070245133A1 Method and Device for Switching Between at Least Two Operating Modes of a Processor Unit 审中-公开
标题翻译：用于在处理器单元的至少两种操作模式下切换的方法和装置
公开(公告)号：US20070245133A1
公开(公告)日：2007-10-18
申请号：US10577009
申请日：2004-08-20
申请人： Reinhard Weiberle , Thomas Kottke , Andreas Steininger
发明人： Reinhard Weiberle , Thomas Kottke , Andreas Steininger
IPC分类号： G06F9/318
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/30189 , G06F9/3885 , G06F2201/845
摘要： A method and a device are described for switching between at least two operating modes of a processor unit including at least two execution units for running programs, at least one identifier being assigned to at least the programs which differentiates between the at least two operating modes, and switching between the operating modes is performed as a function of the identifier such that the processor unit runs the programs according to the assigned operating mode.
摘要翻译：描述了一种方法和装置，用于在包括用于运行程序的至少两个执行单元的处理器单元的至少两个操作模式之间进行切换，至少一个标识符被分配给至少区分至少两个操作模式的程序，并且根据所述标识符执行所述操作模式之间的切换，使得所述处理器单元根据所分配的操作模式来运行所述程序。

3. 发明申请

US20090024908A1 Method for error registration and corresponding register 审中-公开
标题翻译：错误注册方法和相应的寄存器
公开(公告)号：US20090024908A1
公开(公告)日：2009-01-22
申请号：US11659308
申请日：2005-08-01
申请人： Thomas Kottke , Andreas Steininger , Christian El Salloum
发明人： Thomas Kottke , Andreas Steininger , Christian El Salloum
IPC分类号： G06F11/07
CPC分类号： G06F11/1679 , G06F11/0739 , G06F11/0772 , G06F11/0793 , G06F11/0796 , G06F2201/845
摘要： A method for error registration and a register which is assigned to a dual-computer system, information in the form of bits being stored in the register, the dual-computer system including an error-detection mechanism, and the bits in the register as error bits representing at least one error signal of the error-detection mechanism.
摘要翻译：一种用于错误注册的方法和分配给双计算机系统的寄存器，以比特形式存储在寄存器中的信息，双计算机系统包括错误检测机制，并且寄存器中的位作为错误表示错误检测机构的至少一个误差信号的位。

4. 发明申请

US20070283061A1 Method for Delaying Accesses to Date and/or Instructions of a Two-Computer System, and Corresponding Delay Unit 审中-公开
标题翻译：延迟访问双计算机系统的日期和/或指令的方法以及相应的延迟单元
公开(公告)号：US20070283061A1
公开(公告)日：2007-12-06
申请号：US11659622
申请日：2005-08-03
申请人： Bernd Mueller , Werner Harter , Thomas Kottke , Andreas Steininger
发明人： Bernd Mueller , Werner Harter , Thomas Kottke , Andreas Steininger
IPC分类号： G06F13/42
CPC分类号： G06F11/1641 , G06F11/1679 , G06F11/1695 , G06F2201/845
摘要： A delay unit and a method for delaying accesses to data and/or instructions of a two-computer system having a first and a second computer, the first and the second computer operating with a time offset, and the delay unit being embodied in such a way that that time offset is compensated for in the two-computer system in the context of the accesses to data and/or instructions in at least one of the two computers, as well as a method and delay unit for delaying accesses to data and/or instructions of a computer system having error discovery mechanisms for error detection, wherein the time span between undelayed access to data and/or instructions and error detection is compensated for.
摘要翻译：一种用于延迟对具有第一和第二计算机的双计算机系统的数据和/或指令的访问的延迟单元和方法，所述第一和第二计算机以时间偏移量操作，并且所述延迟单元被实施为在两计算机系统中在对两个计算机中的至少一个访问数据和/或指令的上下文中补偿该时间偏移的方式以及用于延迟访问数据和/ 或具有用于错误检测的错误发现机制的计算机系统的指令，其中补偿对数据和/或指令的无延迟访问与错误检测之间的时间间隔。

5. 发明申请

US20060190702A1 Device and method for correcting errors in a processor having two execution units 审中-公开
标题翻译：用于校正具有两个执行单元的处理器中的错误的装置和方法
公开(公告)号：US20060190702A1
公开(公告)日：2006-08-24
申请号：US11293385
申请日：2005-12-02
申请人： Werner Harter , Thomas Kottke , Yorck Collani , Andreas Steininger , Christian Salloum
发明人： Werner Harter , Thomas Kottke , Yorck Collani , Andreas Steininger , Christian Salloum
IPC分类号： G06F15/00
CPC分类号： G06F11/165 , G06F11/10 , G06F11/1407 , G06F11/1641 , G06F11/1654 , G06F11/1658 , G06F11/1695
摘要： A method and a device for correcting errors in a processor having two execution units as well as a corresponding processor, in which registers are provided in which instructions and/or associated information can be stored, the instructions being processed redundantly in both execution units and comparison means being included, and being such that by comparing the instructions and/or the associated information a deviation and thus an error is detected, a division of the registers of the processor into first registers and second registers being provided, the first registers being such that a specifiable state of the processor and contents of the second registers are derivable from them, means for a rollback being included, which are such that at least one instruction and/or the information in the first registers are rolled back and are executed anew and/or restored.
摘要翻译：一种用于校正具有两个执行单元的处理器中的错误的方法和装置以及相应的处理器，其中提供了可以存储指令和/或相关信息的寄存器，在两个执行单元中冗余处理的指令和比较并且通过比较指令和/或相关信息，检测出偏差并因此检测到错误，将处理器的寄存器划分为提供的第一寄存器和第二寄存器，第一寄存器使得处理器的可指定状态和第二寄存器的内容可从它们导出，包括回滚的装置，这些装置使得至少一个指令和/或第一寄存器中的信息被回滚并重新执行和/ 或恢复。

6. 发明申请

US20090102534A1 Decentralised fault-tolerant clock pulse generation in vlsi chips 失效
标题翻译： vlsi芯片中的分散式容错时钟脉冲生成
公开(公告)号：US20090102534A1
公开(公告)日：2009-04-23
申请号：US11630268
申请日：2005-07-18
申请人： Ulrich Schmid , Andreas Steininger
发明人： Ulrich Schmid , Andreas Steininger
IPC分类号： G06F1/04
CPC分类号： G06F11/1604 , G06F1/04
摘要： The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs), in which an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, and each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it, and further all local clock pulses are synchronized with respect to frequency in an assured manner, and a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy, and the system clock pulse automatically achieves the maximum possible frequency. The invention further relates to such a hardware system.
摘要翻译：本发明涉及一种在硬件系统中分布式容错时钟脉冲生成的方法，其中系统时钟脉冲通过多个互通的容错时钟脉冲同步算法（TS-Algs）在分布中产生，其中任意通过用户定义和永久网络（TS-Net）的瞬态故障敏感的时钟脉冲信号和每个TS-Alg之间的这种TS-Alg交换信息的数量被分配给一个或多个功能单元（Fu1， Fu2，...），其本地时钟脉冲由其产生，并且进一步所有本地时钟脉冲以有保证的方式相对于频率同步，并且指定数量的瞬态和/或永久故障可能发生在TS- Algs或TS-Net，不会对时钟脉冲产生和/或同步精度产生不利影响，系统时钟脉冲自动实现最大可能的频率。本发明还涉及这种硬件系统。

7. 发明授权

US07791394B2 Decentralised fault-tolerant clock pulse generation in VLSI chips 失效
标题翻译： VLSI芯片中的分散式容错时钟脉冲产生
公开(公告)号：US07791394B2
公开(公告)日：2010-09-07
申请号：US11630268
申请日：2005-07-18
申请人： Ulrich Schmid , Andreas Steininger
发明人： Ulrich Schmid , Andreas Steininger
IPC分类号： G06F1/04
CPC分类号： G06F11/1604 , G06F1/04
摘要： The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs), in which an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, and each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it, and further all local clock pulses are synchronized with respect to frequency in an assured manner, and a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy, and the system clock pulse automatically achieves the maximum possible frequency. The invention further relates to such a hardware system.
摘要翻译：本发明涉及一种在硬件系统中分布式容错时钟脉冲生成的方法，其中系统时钟脉冲通过多个互通的容错时钟脉冲同步算法（TS-Algs）在分布中产生，其中任意通过用户定义和永久网络（TS-Net）的瞬时故障敏感的时钟脉冲信号和每个TS-Alg之间的这种TS-Alg交换信息的数量被分配给一个或多个功能单元（Fu1， Fu2，...），其本地时钟脉冲由其产生，并且进一步所有本地时钟脉冲以有保证的方式相对于频率同步，并且指定数量的瞬态和/或永久故障可能发生在TS- Algs或TS-Net，不会对时钟脉冲产生和/或同步精度产生不利影响，系统时钟脉冲自动实现最大可能的频率。本发明还涉及这种硬件系统。

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