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1. 发明申请

US20090166749A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090166749A1
公开(公告)日：2009-07-02
申请号：US12233055
申请日：2008-09-18
申请人： Reika ICHIHARA , Yoshinori Tsuchiya , Hiroki Tanaka , Masahiko Yoshiki , Masato Koyama
发明人： Reika ICHIHARA , Yoshinori Tsuchiya , Hiroki Tanaka , Masahiko Yoshiki , Masato Koyama
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： A semiconductor device includes n- and p-type semiconductor regions separately formed on a substrate, an interlayer insulator formed on the substrate and having first and second trenches formed to reach the n- and p-type regions. There are further included first and second gate insulators formed inside of the first and second trenches, a first metal layer formed inside of the first trench via the first gate insulator, a second metal layer formed in a thickness of 1 monolayer or more and 1.5 nm or less inside of the second trench via the second gate insulator, a third metal layer formed on the second metal layer and containing at least one of a simple substance, a nitride, a carbide and an oxide of at least one metal element of alkaline earth metal elements and group III elements, first and second source/drain regions formed on the n- and p-type regions.
摘要翻译：半导体器件包括分别形成在衬底上的n型和p型半导体区，形成在衬底上的层间绝缘体，并且具有形成为达到n型和p型区的第一和第二沟槽。还包括形成在第一和第二沟槽内的第一和第二栅极绝缘体，经由第一栅极绝缘体形成在第一沟槽内部的第一金属层，形成为厚度为1单层或更多和1.5nm的第二金属层或更少的内部经由所述第二栅极绝缘体，形成在所述第二金属层上并且包含至少一种碱土金属元素的单质，氮化物，碳化物和氧化物中的至少一种的第三金属层金属元素和III族元素，形成在n型和p型区上的第一和第二源/漏区。

2. 发明申请

US20080237727A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20080237727A1
公开(公告)日：2008-10-02
申请号：US11965563
申请日：2007-12-27
申请人： Reika ICHIHARA , Yoshinori Tsuchiya , Masato Koyama
发明人： Reika ICHIHARA , Yoshinori Tsuchiya , Masato Koyama
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842
摘要： The present invention provides a CMIS device that achieves a low threshold voltage by use of a metal gate superior in the resistance to annealing in a reducing atmosphere. The CMIS device includes a substrate, PMISFET and NMISFET. THE PMISFET includes: an N-type semiconductor layer formed on the substrate; first source/drain regions formed in the N-type semiconductor layer; a first gate insulating film formed on the N-type semiconductor layer between the first source/drain regions; a carbon layer formed on the first gate insulating film and having a thickness of 5 nanometers or smaller; a first gate electrode formed on the carbon layer and including a metal.
摘要翻译：本发明提供了一种CMIS器件，其通过使用在还原气氛中的退火电阻优异的金属栅极来实现低阈值电压。 CMIS器件包括衬底，PMISFET和NMISFET。 PMISFET包括：形成在衬底上的N型半导体层; 形成在N型半导体层中的第一源/漏区; 形成在所述第一源极/漏极区域之间的所述N型半导体层上的第一栅极绝缘膜; 形成在所述第一栅极绝缘膜上并具有5纳米或更小的厚度的碳层; 形成在碳层上并包括金属的第一栅电极。

3. 发明申请

US20120049289A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120049289A1
公开(公告)日：2012-03-01
申请号：US13290552
申请日：2011-11-07
申请人： Reika ICHIHARA , Masato Koyama
发明人： Reika ICHIHARA , Masato Koyama
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823842 , H01L29/4966 , H01L29/518 , H01L29/6659
摘要： A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.
摘要翻译：半导体器件包括在半导体衬底上形成的pMISFET和nMIS。 pMISFET在半导体衬底上包括第一源极/漏极区域，在其间形成的第一栅极电介质，堆叠在第一栅极电介质上的第一下部和上部金属层，包含至少一个属于IIA族金属元素的第一上部金属层和IIIA。 nMISFET在半导体衬底上包括第二源极/漏极区域，在其间形成的第二栅极电介质，堆叠在第二栅极电介质上的第二下部和上部金属层，以及基本上具有与第一上部金属相同的组成的第二上部金属层层。第一下金属层比第二下金属层厚，并且包含在第一栅极电介质中的金属元素的原子密度低于包含在第二栅极电介质中的金属元素的原子密度。

4. 发明申请

US20110275184A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20110275184A1
公开(公告)日：2011-11-10
申请号：US13184116
申请日：2011-07-15
申请人： Reika ICHIHARA , Yoshinori TSUCHIYA , Masato KOYAMA , Akira NISHIYAMA
发明人： Reika ICHIHARA , Yoshinori TSUCHIYA , Masato KOYAMA , Akira NISHIYAMA
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分的第一电介质面向第一金属栅电极。

5. 发明申请

US20110266632A1 Semiconductor Device 有权
公开(公告)号：US20110266632A1
公开(公告)日：2011-11-03
申请号：US13184159
申请日：2011-07-15
申请人： Reika ICHIHARA , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika ICHIHARA , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

6. 发明申请

US20080135944A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080135944A1
公开(公告)日：2008-06-12
申请号：US11857197
申请日：2007-09-18
申请人： Reika ICHIHARA , Yoshinori Tsuchiya , Hiroki Tanaka , Masato Koyama
发明人： Reika ICHIHARA , Yoshinori Tsuchiya , Hiroki Tanaka , Masato Koyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/823864
摘要： A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.
摘要翻译：半导体器件在衬底上具有n沟道MIS晶体管和p沟道MIS晶体管。 n沟道MIS晶体管包括形成在基板上的p型半导体区域，通过p型半导体区域上方的栅极绝缘膜形成并且为单层以上且3nm以下的下层栅电极以及形成在下层栅电极上的上层栅电极，其平均电负性比下层栅电极的平均电负性小0.1或更小。 p沟道MIS晶体管包括形成在衬底上的n型半导体区域和通过n型半导体区域上方的栅极绝缘膜形成并由与上层相同的金属材料制成的栅电极栅电极。

7. 发明申请

US20130250654A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20130250654A1
公开(公告)日：2013-09-26
申请号：US13601570
申请日：2012-08-31
申请人： Kikuko SUGIMAE , Reika ICHIHARA
发明人： Kikuko SUGIMAE , Reika ICHIHARA
IPC分类号： G11C13/00
CPC分类号： G11C13/0002 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2213/71 , G11C2213/73
摘要： A non-volatile semiconductor memory device includes a cell array layer including a first wire, a memory cell, and a second wire, and a control circuit. When performing set operation for setting the memory cell to a low resistance state, until a resistance value of the memory cell becomes lower than a predetermined resistance value, the control circuit repeating: applying a first voltage for setting to the memory cell; and a verify read verifying that the resistance value of the memory cell has become lower than the predetermined resistance value. After the verify read, the control circuit applies a second voltage having a different polarity from the first voltage to the memory cell before applying the first voltage that follows.
摘要翻译：非挥发性半导体存储器件包括包括第一布线，存储单元和第二布线的单元阵列层以及控制电路。当进行用于将存储单元设置为低电阻状态的设定操作，直到存储单元的电阻值变得低于预定电阻值为止，控制电路重复：向存储单元施加用于设置的第一电压; 以及验证存储单元的电阻值已经变得低于预定电阻值的验证读取。在验证读取之后，控制电路在施加随后的第一电压之后，将具有与第一电压不同的极性的第二电压施加到存储单元。

8. 发明申请

US20120320662A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120320662A1
公开(公告)日：2012-12-20
申请号：US13597318
申请日：2012-08-29
申请人： Reika ICHIHARA , Takayuki Tsukamoto
发明人： Reika ICHIHARA , Takayuki Tsukamoto
IPC分类号： G11C11/00
CPC分类号： G11C11/00 , G11C2013/0083
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.
摘要翻译：根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。多个第二线延伸以与第一线相交。多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。控制电路被配置为控制施加到存储器单元的电压。控制电路在成形操作期间向可变电阻器施加第一脉冲电压。此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。

9. 发明申请

US20110216574A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110216574A1
公开(公告)日：2011-09-08
申请号：US12886931
申请日：2010-09-21
申请人： Reika ICHIHARA , Takayuki Tsukamoto
发明人： Reika ICHIHARA , Takayuki Tsukamoto
IPC分类号： G11C11/00
CPC分类号： G11C11/00 , G11C2013/0083
摘要： A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.
摘要翻译：根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。多个第二线延伸以与第一线相交。多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。控制电路被配置为控制施加到存储器单元的电压。控制电路在成形操作期间向可变电阻器施加第一脉冲电压。此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。

10. 发明申请

US20120063193A1 MULTI-LEVEL RESISTANCE CHANGE MEMORY 有权
标题翻译：多层电阻变化记忆
公开(公告)号：US20120063193A1
公开(公告)日：2012-03-15
申请号：US13053677
申请日：2011-03-22
申请人： Reika ICHIHARA
发明人： Reika ICHIHARA
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0092 , G11C2211/562 , G11C2211/563 , G11C2213/76 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1675
摘要： According to one embodiment, a multi-level resistance change memory includes a memory cell includes first and second resistance change films connected in series, and a capacitor connected in parallel to the first resistance change film, a voltage pulse generating circuit generating a first voltage pulse with a first pulse width to divide a voltage of the first voltage pulse into the first and second resistance change films based on a resistance ratio thereof, and generating a second voltage pulse with a second pulse width shorter than the first pulse width to apply a voltage of the second voltage pulse to the second resistance change film by a transient response of the capacitor, and a control circuit which is stored multi-level data to the memory cell by using the first and second voltage pulses in a writing.
摘要翻译：根据一个实施例，多电平电阻变化存储器包括存储单元，包括串联连接的第一和第二电阻变化膜以及并联连接到第一电阻变化膜的电容器，产生第一电压脉冲的电压脉冲发生电路具有第一脉冲宽度，以基于其电阻比将第一电压脉冲的电压分成第一和第二电阻变化膜，并产生具有比第一脉冲宽度短的第二脉冲宽度的第二电压脉冲，以施加电压通过电容器的瞬态响应将第二电压脉冲施加到第二电阻变化膜;以及控制电路，其通过在写入中使用第一和第二电压脉冲将多电平数据存储到存储单元。

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