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1. 发明专利

JP2006013470A Chip protection device and method 审中-公开
标题翻译：芯片保护装置和方法
公开(公告)号：JP2006013470A
公开(公告)日：2006-01-12
申请号：JP2005150030
申请日：2005-05-23
申请人： Realtek Semiconductor Corp , リアルテックセミコンダクターコーポレイション
发明人： HUANG CHEN-CHIH , YEH TA-HSUN
IPC分类号： H01L21/822 , G06K19/073 , H01L21/82 , H01L27/04 , H03K5/19 , H04K1/00
CPC分类号： G06K19/07345 , G06K19/073
摘要： PROBLEM TO BE SOLVED: To provide a chip protection device to protect chips of an integrated circuit and its method.
SOLUTION: The protection device located in the chips includes a decoding circuit to decode a password to output a decoding signal and a security circuit joined with the decoding circuit to output a enabling signal according to the decoding signal. The integrated circuit enables the desired function of the chips by the enabling signal. Thus, the protection device prevents the chips from being reproduced.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种保护集成电路芯片的芯片保护装置及其方法。解决方案：位于芯片中的保护装置包括解码电路，用于解码密码以输出解码信号，以及与解码电路连接的安全电路，以根据解码信号输出使能信号。集成电路通过使能信号实现芯片的期望功能。因此，保护装置防止芯片被再现。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2005203736A Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：JP2005203736A
公开(公告)日：2005-07-28
申请号：JP2004284478
申请日：2004-09-29
申请人： Realtek Semiconductor Corp , 瑞▲いー▼半導體股▲ふん▼有限公司
发明人： YEH TA-HSUN , LIN YUNG-HAO , JEAN YUH-SHENG
IPC分类号： H01L29/70 , H01L21/33 , H01L21/822 , H01L27/02 , H01L27/04 , H02H9/00
CPC分类号： H01L27/0259 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an electrostatic discharge protection circuit which has a low leak current, a high breakdown voltage, high current driving capability, and a low parasitic capacitance. SOLUTION: The electrostatic discharge protection circuit includes a first transistor group coupled to a first operating voltage and a third operating voltage, a second transistor group coupled to a second operating voltage and a fourth operating voltage, a first detector circuit which is electrically connected between the first operating voltage and the second operating voltage and detects an electrostatic voltage to generate a first trigger signal, a first electrostatic discharge circuit electrically connected between the first operating voltage and the second operating voltage, a second detector circuit which is electrically connected between the third operating voltage and the fourth operating voltage and detects an electrostatic voltage to generate a second trigger signal, and a second electrostatic discharge circuit electrically connected between the third operating voltage and the fourth operating voltage. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种具有低漏电流，高击穿电压，高电流驱动能力和低寄生电容的静电放电保护电路。解决方案：静电放电保护电路包括耦合到第一工作电压和第三工作电压的第一晶体管组，耦合到第二工作电压和第四工作电压的第二晶体管组，第一检测器电路，其是电连接在第一工作电压和第二工作电压之间并且检测静电电压以产生第一触发信号，电连接在第一工作电压和第二工作电压之间的第一静电放电电路，第二检测器电路电连接在第三工作电压和第四工作电压，并且检测静电电压以产生第二触发信号，以及电连接在第三工作电压和第四工作电压之间的第二静电放电电路。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2007110129A Integrated inductor 审中-公开
标题翻译：集成电感器
公开(公告)号：JP2007110129A
公开(公告)日：2007-04-26
申请号：JP2006277978
申请日：2006-10-11
申请人： Realtek Semiconductor Corp , 瑞▲いー▼半導體股▲ふん▼有限公司
发明人： YEH TA-HSUN , JEAN YUH-SHENG
IPC分类号： H01L21/822 , H01L21/3205 , H01L23/52 , H01L27/04
CPC分类号： H01F17/0006 , H01F27/34 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an integrated inductor of high quality at low cost, in which the manufacturing process is simplified. SOLUTION: The inductor includes: a metal layer pattern; a rearrangement layer pattern formed as the upper layer of the metal layer pattern; and a via layer pattern which is formed between the metal layer pattern and the rearrangement layer pattern, and conductively connected to the metal layer pattern and the rearrangement layer pattern. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：以低成本提供高质量的集成电感器，其中制造过程被简化。电感器包括：金属层图案; 形成为金属层图案的上层的重排层图案; 以及形成在金属层图案和重排层图案之间并且导电连接到金属层图案和重排层图案的通孔层图案。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2005123570A Static discharge protective circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：JP2005123570A
公开(公告)日：2005-05-12
申请号：JP2004200757
申请日：2004-07-07
申请人： Realtek Semiconductor Corp , 瑞▲いー▼半導體股▲ふん▼有限公司
发明人： LIN YUNG-HAO , TSAUR TAY-HER , YEH TA-HSUN , LEE CHAO-CHENG
IPC分类号： H01L27/04 , H01L21/822 , H01L23/60 , H01L27/02 , H01L27/06 , H02H9/00
CPC分类号： H01L27/0266
摘要： PROBLEM TO BE SOLVED: To provide a static discharge protective circuit improving static discharge protecting capacity by using a stack coupling device in order to solve various matters due to conventional technologies.
SOLUTION: A static discharge protective circuit provided among a plurality of reference points includes a clamping device coupled between two reference points of a plurality of reference points, a stack coupling device coupled between the clamping device and one reference point, and a resistive device coupled between the stack coupling device and one reference point.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种通过使用堆叠耦合装置来提高静电放电保护能力的静电放电保护电路，以解决由于常规技术而引起的各种问题。解决方案：在多个参考点之间提供的静电放电保护电路包括耦合在多个参考点的两个参考点之间的夹紧装置，耦合在夹紧装置和一个参考点之间的叠置耦合装置，以及电阻耦合在堆叠耦合装置和一个参考点之间的装置。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

DE102004023309B4 Kaskadierte Diodenstruktur mit tiefer n-Wanne und Verfahren zum Herstellen derselben 未知
公开(公告)号：DE102004023309B4
公开(公告)日：2016-06-30
申请号：DE102004023309
申请日：2004-05-11
申请人： REALTEK SEMICONDUCTOR CORP
发明人： YEH TA-HSUN , LEE CHAO-CHENG , TSAUR TAY-HER
IPC分类号： H01L27/082 , H01L21/822 , H01L23/62 , H01L27/02 , H01L27/08
摘要： Kaskadierte Diodenstruktur mit: – einem p-Substrat (51); – einer im p-Substrat (51) ausgebildeten tiefen n-Wanne (52); – mehreren Diodenelementen (D1, ... Dm), die auf der tiefen n-Wanne (52) ausgebildet sind und von denen jedes eine auf der tiefen n-Wanne (52) ausgebildete p-Wanne (53), einen auf der p-Wanne (53) ausgebildeten stark dotierten p-Bereich (54) und einen auf der p-Wanne ausgebildeten stark dotierten n-Bereich (55) aufweist; und – mehreren Verbindungsteilen zum Kaskadieren der mehreren Diodenelemente (D1, ... Dm).

6. 发明专利

DE102004031706A1 未知
公开(公告)号：DE102004031706A1
公开(公告)日：2005-02-03
申请号：DE102004031706
申请日：2004-06-30
申请人： REALTEK SEMICONDUCTOR CORP
发明人： YEH TA-HSUN , LEE CHAO-CHENG , TSAUR TAY-HER
IPC分类号： H01L23/60 , H01L27/02 , H01L27/082 , H02H9/08
摘要： An ESD clamp circuit includes an ESD detecting unit and a discharge circuit with a longitudinal BJT. The longitudinal BJT is formed on a P-type substrate and includes a deep N-well formed on the P-type substrate, a P-well formed on parts of the deep N-well, a N-well formed on the deep N-well surrounding the P-well, a first N+ region formed on parts of the P-well and electrically coupled to a first voltage, a P+ region formed on the P-well surrounding the first N+ region and electrically coupled to a trigger signal, and a second N+ region formed on the N-well and electrically coupled to a second voltage. In the structure of the longitudinal BJT, the leakage current can be decreased, the current gain can be increased, and the dimension of the ESD clamp circuit can be reduced.

7. 发明专利

DE102004023309A1 Cascaded diode structure for use in ESD clamp circuit, has deep N-well formed on P-type substrate, set of elemental diodes formed on deep N-well, and set of connecting parts to cascade elemental diodes 未知
公开(公告)号：DE102004023309A1
公开(公告)日：2005-02-10
申请号：DE102004023309
申请日：2004-05-11
申请人： REALTEK SEMICONDUCTOR CORP
发明人： YEH TA-HSUN , LEE CHAO-CHENG , TSAUR TAY-HER
IPC分类号： H01L27/02 , H01L27/08 , H01L27/082 , H01L21/822 , H01L23/62
摘要： The structure has a deep N-well (52) formed on a P-type substrate. A set of elemental diodes are formed on the deep N-well. Each of the elemental diodes comprises a P-well (53) formed on the deep N-well. A heavily doped P-type region (54) is formed on the P-well, and a heavily doped N-type region is formed on the P-well. A set of connecting parts cascade the set of elemental diodes. Independent claims are also included for the following: (A) a method for forming a cascaded diode structure (B) an ESD clamp circuit comprising a cascaded diode structure.

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