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1. 发明授权

US07787222B2 Over-voltage protection for voltage regulator modules of a parallel power system 有权
标题翻译：并联电力系统稳压器模块的过电压保护
公开(公告)号：US07787222B2
公开(公告)日：2010-08-31
申请号：US11769242
申请日：2007-06-27
申请人： Kevin R. Covi , Raymond J. Harrington , Robert P. Makowicki , Steven G. Shevach , Dale F. Soreson , Brain C. Tucker
发明人： Kevin R. Covi , Raymond J. Harrington , Robert P. Makowicki , Steven G. Shevach , Dale F. Soreson , Brain C. Tucker
IPC分类号： H02H3/20
CPC分类号： H02M3/1584 , H02M1/32
摘要： A protection circuit for a parallel power system having at least two parallel coupled voltage regulators is disclosed. The protection circuit includes at least two isolation control circuits, each control circuit being coupled to a respective voltage regulator. Each isolation control circuit includes a current sense circuit for sensing current polarity at an output of the respective voltage regulator, and a controller for automatically isolating the respective voltage regulator when an over-voltage condition exists at an output of the parallel power system and a positive current polarity is sensed at the output of the respective voltage regulator. The at least two isolation control circuits isolate only a voltage regulator having positive current outflow during the over-voltage condition. In one embodiment, each isolation control circuit further includes an over-voltage detection circuit for detecting when the over-voltage condition exists at the output of the parallel power system.
摘要翻译：公开了一种具有至少两个并联耦合电压调节器的并联电力系统的保护电路。保护电路包括至少两个隔离控制电路，每个控制电路耦合到相应的电压调节器。每个隔离控制电路包括用于检测各个电压调节器的输出端的电流极性的电流检测电路，以及当在并联电力系统的输出端存在过电压状态时，用于自动隔离相应电压调节器的控制器，在相应的电压调节器的输出处感测出电流极性。至少两个隔离控制电路在过电压状态期间仅隔离具有正电流流出的电压调节器。在一个实施例中，每个隔离控制电路还包括过电压检测电路，用于检测并联电力系统的输出端何时存在过电压状态。

2. 发明授权

US07644216B2 System and method for providing an adapter for re-use of legacy DIMMS in a fully buffered memory environment 失效
标题翻译：用于提供用于在完全缓冲的存储器环境中重复使用传统DIMMS的适配器的系统和方法
公开(公告)号：US07644216B2
公开(公告)日：2010-01-05
申请号：US11735677
申请日：2007-04-16
申请人： Gerald J. Fahr , Raymond J. Harrington , Roger A. Rippens , Donald J. Swietek
发明人： Gerald J. Fahr , Raymond J. Harrington , Roger A. Rippens , Donald J. Swietek
IPC分类号： H05K7/10
CPC分类号： G06F13/16 , G06F13/385
摘要： A system and method for providing an adapter for re-use of legacy DIMMS in a fully buffered memory environment. The system includes a memory adapter card having two rows of contacts along a leading edge of a length of the card. The rows of contacts are adapted to be inserted into a socket that is connected to a daisy chain high-speed memory bus via a packetized multi-transfer interface. The memory adapter card also includes a socket installed on the trailing edge of the card. In addition, the memory adapter card includes a hub device for converting the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. In addition, the hub device converts the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. The hub device also converts the parallel interface into the packetized multi-transfer interface.
摘要翻译：一种用于在完全缓冲的存储器环境中提供用于重新使用传统DIMMS的适配器的系统和方法。该系统包括具有沿着卡的长度的前缘的两行触点的存储器适配器卡。触点行适于插入通过分组化的多传输接口连接到菊花链高速存储器总线的插座中。存储器适配器卡还包括安装在卡尾部的插座。此外，存储器适配器卡包括用于将打包的多传输接口转换成具有定时和接口级别的并行接口的集线器设备，该定时和接口级别可与具有插入插座的并行接口的存储器模块一起操作。此外，集线器设备将打包的多传输接口转换成具有定时和接口级别的并行接口，该定时和接口级别可与具有插入插座的并行接口的存储器模块一起操作。集线器设备还将并行接口转换为打包的多传输接口。

3. 发明申请

US20080256281A1 SYSTEM AND METHOD FOR PROVIDING AN ADAPTER FOR RE-USE OF LEGACY DIMMS IN A FULLY BUFFERED MEMORY ENVIRONMENT 失效
标题翻译：提供适配器的系统和方法，用于在完全缓冲的存储器环境中重新使用代码
公开(公告)号：US20080256281A1
公开(公告)日：2008-10-16
申请号：US11735677
申请日：2007-04-16
申请人： Gerald J. Fahr , Raymond J. Harrington , Roger A. Rippens , Donald J. Swietek
发明人： Gerald J. Fahr , Raymond J. Harrington , Roger A. Rippens , Donald J. Swietek
IPC分类号： G06F13/14
CPC分类号： G06F13/16 , G06F13/385
摘要： A system and method for providing an adapter for re-use of legacy DIMMS in a fully buffered memory environment. The system includes a memory adapter card having two rows of contacts along a leading edge of a length of the card. The rows of contacts are adapted to be inserted into a socket that is connected to a daisy chain high-speed memory bus via a packetized multi-transfer interface. The memory adapter card also includes a socket installed on the trailing edge of the card. In addition, the memory adapter card includes a hub device for converting the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. In addition, the hub device converts the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. The hub device also converts the parallel interface into the packetized multi-transfer interface.
摘要翻译：一种用于在完全缓冲的存储器环境中提供用于重新使用传统DIMMS的适配器的系统和方法。该系统包括具有沿着卡的长度的前缘的两行触点的存储器适配器卡。触点行适于插入通过分组化的多传输接口连接到菊花链高速存储器总线的插座中。存储器适配器卡还包括安装在卡尾部的插座。此外，存储器适配器卡包括用于将打包的多传输接口转换成具有定时和接口级别的并行接口的集线器设备，该定时和接口级别可与具有插入插座的并行接口的存储器模块一起操作。此外，集线器设备将打包的多传输接口转换成具有定时和接口级别的并行接口，该定时和接口级别可与具有插入插座的并行接口的存储器模块一起操作。集线器设备还将并行接口转换为打包的多传输接口。

4. 发明授权

US06515840B2 Solid state circuit breaker with current overshoot protection 有权
公开(公告)号：US06515840B2
公开(公告)日：2003-02-04
申请号：US09794938
申请日：2001-02-27
申请人： Kevin Covi , Robert B. Schlak , Raymond J. Harrington , Edward J. Seminaro
发明人： Kevin Covi , Robert B. Schlak , Raymond J. Harrington , Edward J. Seminaro
IPC分类号： H02H308
CPC分类号： H02H3/087 , H02H3/025 , H02H3/093 , H02H3/44
摘要： A solid state circuit breaker is disclosed for use in connection with a voltage bus, the voltage bus supplying electrical current to a load. The solid state circuit breaker includes a current controller for controlling the magnitude of current supplied by the voltage bus. A first current sensor senses the magnitude of the electrical current supplied by the voltage bus, the first current sensor having an output in communication with the current controller. An inductor is included within the first current sensor, the inductor providing a back electromotive force on the voltage bus. The back electromotive force is proportional to the rate of change of current flowing through the voltage bus.

5. 发明授权

US09021097B2 Unified cloud computing infrastructure to manage and deploy physical and virtual environments 有权
公开(公告)号：US09021097B2
公开(公告)日：2015-04-28
申请号：US13466224
申请日：2012-05-08
申请人： Rohith K. Ashok , Thomas M. Brey , Raymond J. Harrington , Matt R. Hogstrom , Matthew J. Sheard
发明人： Rohith K. Ashok , Thomas M. Brey , Raymond J. Harrington , Matt R. Hogstrom , Matthew J. Sheard
IPC分类号： G06F15/173 , G06F3/00 , G06F9/50 , H04L29/08
CPC分类号： G06F9/5072 , H04L41/0803 , H04L41/5096 , H04L67/10
摘要： A method, system and computer program product for managing and deploying physical and virtual environments across multiple hardware platforms. A single unit, referred to herein as a cloud construction block, contains both the hardware and software components used to build a cloud computing environment. By having such a single unit contain both the hardware and software components needed to build a cloud computing environment, the user no longer needs to purchase and integrate different hardware and software components. Furthermore, the cloud construction block contains modular pieces of hardware, such as compute hardware, memory hardware, storage hardware and network hardware, that are integrated with management software configured to manage both the hardware and the cloud computing environment in a seamlessly integrated package. Since there is a single management system, the management software allows the user to manage the modular pieces of hardware via a single user interface.

6. 发明申请

US20110257802A1 POWER DISTRIBUTION CONSIDERING COOLING NODES 失效
标题翻译：考虑冷却点的功率分配
公开(公告)号：US20110257802A1
公开(公告)日：2011-10-20
申请号：US12762166
申请日：2010-04-16
申请人： ANDREAS BIESWANGER , Andrew J. Geissler , Raymond J. Harrington , Hye-Young McCreary , Freeman Leigh Rawson, III , Malcolm Scott Ware
发明人： ANDREAS BIESWANGER , Andrew J. Geissler , Raymond J. Harrington , Hye-Young McCreary , Freeman Leigh Rawson, III , Malcolm Scott Ware
IPC分类号： G06F1/32 , G05D23/19
CPC分类号： G06F1/3203 , G06F1/20
摘要： A method, system, and computer usable program product for power distribution considering cooling nodes in a data processing environment. A power demand of a data processing environment is determined for a period. The data processing environment includes a set of computing nodes and cooling nodes. A determination is made that the power demand will exceed a limit on electrical power available to the data processing environment for the period if the computing nodes and the cooling nodes in the data processing environment are operated in a first configuration. A first amount of power is redistributed from a cooling node in the data processing environment to a computing node in the data processing environment such that a temperature related performance threshold of a subset of computing nodes is at least met.
摘要翻译：一种考虑到数据处理环境中的冷却节点进行配电的方法，系统和计算机可用程序产品。数据处理环境的功率需求被确定一段时间。数据处理环境包括一组计算节点和冷却节点。如果数据处理环境中的计算节点和冷却节点在第一配置中操作，则确定功率需求将超过对于该周期的数据处理环境可用的电力的限制。将第一数量的功率从数据处理环境中的冷却节点重新分配到数据处理环境中的计算节点，使得至少满足计算节点的子集的温度相关的性能阈值。

7. 发明申请

US20090125659A1 Inter-Integrated Circuit (12C) Slave with Read/Write Access to Random Access Memory 审中-公开
标题翻译：具有读/写访问随机存取存储器的内部集成电路（12C）从机
公开(公告)号：US20090125659A1
公开(公告)日：2009-05-14
申请号：US12354979
申请日：2009-01-16
申请人： Eileen M. Behrendt , Jeffrey R. Biamonte , Raymond J. Harrington , Timothy M. Trifilo
发明人： Eileen M. Behrendt , Jeffrey R. Biamonte , Raymond J. Harrington , Timothy M. Trifilo
IPC分类号： G06F13/40
CPC分类号： G06F13/4291
摘要： A program and device for data access via an inter-integrated circuit (I2C) protocol are provided, which includes receiving an I2C read command at an I2C slave device from an I2C master device, and the I2C read command at the I2C slave device is altered such that the I2C read command causes stored data to be read from a storage device, being external to the I2C slave device, in place of reading from internal memory of I2C slave device. An I2C write command having master data and a slave device register address is intended to write to the internal memory of the I2C slave device, and I2C write command at the I2C slave device is altered such that the I2C write command causes the master data to write to the storage device, being external to the I2C slave device, in place of writing to internal memory of the I2C slave device.
摘要翻译：提供了通过集成电路（I2C）协议进行数据访问的程序和设备，其中包括从I2C主器件在I2C从器件处接收I2C读命令，I2C从器件上的I2C读命令被更改使得I2C读取命令使存储的数据从I2C从器件外部的存储器件读取，而不是从I2C从器件的内部存储器读取。具有主数据和从器件寄存器地址的I2C写命令旨在写入I2C从器件的内部存储器，I2C从器件上的I2C写命令被更改，使得I2C写命令使主数据写入到I2C从器件外部的存储设备，代替写入I2C从器件的内部存储器。

8. 发明授权

US07522524B2 Employing one or more multiport systems to facilitate servicing of asynchronous communications events 失效
标题翻译：使用一个或多个多端口系统来促进对异步通信事件的维护
公开(公告)号：US07522524B2
公开(公告)日：2009-04-21
申请号：US10834799
申请日：2004-04-29
申请人： Eileen M. Behrendt , Jeffrey R. Biamonte , Raymond J. Harrington
发明人： Eileen M. Behrendt , Jeffrey R. Biamonte , Raymond J. Harrington
IPC分类号： H04L12/50
CPC分类号： G06F13/4022 , G06F13/364 , H04L12/407 , H04L49/1553 , H04L2012/40273
摘要： One or more multiport systems are used to facilitate servicing of asynchronous communications events. A multiport system, such as an open collector multiport system, receives from one of a plurality of source components an asynchronous communications event directed to a target component coupled to the plurality of source components. The multiport system is controlled to provide, at any given time, a communications path between a plurality of ports of the multiport system to service the asynchronous communications event. One or more multiport systems are used to forward the event from the source to the target.
摘要翻译：使用一个或多个多端口系统来促进异步通信事件的服务。多端口系统，例如开放收集器多端口系统，从多个源组件中的一个源接收指向耦合到多个源组件的目标组件的异步通信事件。多端口系统被控制以在任何给定的时间提供多端口系统的多个端口之间的通信路径来服务异步通信事件。一个或多个多端口系统用于将事件从源转发到目标。

9. 发明授权

US06876229B1 Method and system for providing bidirectional asynchronous communication 失效
标题翻译：提供双向异步通信的方法和系统
公开(公告)号：US06876229B1
公开(公告)日：2005-04-05
申请号：US10668488
申请日：2003-09-23
申请人： Daniel J. Barus , Jeffrey R. Biamonte , Raymond J. Harrington , Timothy M. Trifilo
发明人： Daniel J. Barus , Jeffrey R. Biamonte , Raymond J. Harrington , Timothy M. Trifilo
IPC分类号： H04L5/14 , H03K19/0175
CPC分类号： H04L5/1423
摘要： A communication system for establishing bidirectional, asynchronous communication between a first device and a second device. The system includes first asynchronous encoder logic and second asynchronous encoder logic for controlling the state of the communication system such that bi-directional communication is enabled without a direction control line.
摘要翻译：一种用于在第一设备和第二设备之间建立双向异步通信的通信系统。该系统包括用于控制通信系统的状态的第一异步编码器逻辑和第二异步编码器逻辑，使得在没有方向控制线的情况下启用双向通信。

10. 发明授权

US07353308B2 Avoiding oscillation in self-synchronous bi-directional communication system 失效
标题翻译：避免自同步双向通信系统中的振荡
公开(公告)号：US07353308B2
公开(公告)日：2008-04-01
申请号：US11254577
申请日：2005-10-20
申请人： Daniel J. Barus , Eileen M. Behrendt , Jeffrey R. Biamonte , Raymond J. Harrington , Timothy M. Trifilo
发明人： Daniel J. Barus , Eileen M. Behrendt , Jeffrey R. Biamonte , Raymond J. Harrington , Timothy M. Trifilo
IPC分类号： G06F13/00
CPC分类号： G06F13/4077 , H04L5/16
摘要： In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.
摘要翻译：在用于半导体器件之间的通信的双向自同步总线中，提供逻辑延迟作为状态机控制的标志，用于指示总线正在从低状态转变为高状态。逻辑延迟导致总线自适应空闲，直到总线稳定，使其适用于各种总线大小和拓扑。以这种方式，避免了总线的振荡，而不会降低状态机时钟的速度。

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