专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6000014A Software-managed programmable congruence class caching mechanism 失效
标题翻译：软件管理可编程一致级缓存机制
公开(公告)号：US6000014A
公开(公告)日：1999-12-07
申请号：US834490
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08
CPC分类号： G06F12/0864
摘要： A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. Program instructions are loaded in the processor for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes is then defined using a mapping function which operates on the encoded addresses, such that the program instructions may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The program instructions can modify the original addresses by setting a plurality of programmable fields. Application software may provide the program instructions, wherein congruence classes are programmed based on a particular procedure of the application software which is running on the processor, that might otherwise run with excessive "striding" of the cache. Alternatively, operating-system software may monitor allocation of memory blocks in the cache and provides the program instructions to modify the original addresses based on the allocation of the memory blocks, to lessen striding.
摘要翻译：公开了一种在由计算机系统的处理器使用的高速缓存器中提供可编程一致等级的方法。程序指令被加载到处理器中，用于修改存储器件中的存储器块的原始地址以产生编码的地址。然后使用对编码地址进行操作的映射函数来定义多个高速缓存一致等级，使得程序指令可以用于任意地将给定的一个原始地址分配给高速缓存一致性类的特定一个。程序指令可以通过设置多个可编程字段来修改原始地址。应用软件可以提供程序指令，其中根据在处理器上运行的应用软件的特定过程对一致性类进行编程，否则可能以高速缓存的“跨步”运行。或者，操作系统软件可以监视高速缓存中的存储器块的分配，并且提供程序指令以基于存储器块的分配来修改原始地址，以减少跨越。

2. 发明授权

US5983322A Hardware-managed programmable congruence class caching mechanism 失效
标题翻译：硬件管理的可编程一致级缓存机制
公开(公告)号：US5983322A
公开(公告)日：1999-11-09
申请号：US839560
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08
CPC分类号： G06F12/0864
摘要： A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. A logic unit is connected to the cache for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes are then defined using a mapping function which operates on the encoded addresses, such that the logic unit may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The logic unit can modify the original addresses by setting a plurality of programmable fields. The logic unit also can collect information on cache misses, and modify the original addresses in response to the cache miss information. In this manner, a procedure running on the processor and allocating memory blocks to the cache such that the original addresses, if applied to the mapping function, would result in striding of the cache, runs more efficiently by using the encoded addresses to result in less striding of the cache.
摘要翻译：公开了一种在由计算机系统的处理器使用的高速缓存器中提供可编程一致等级的方法。逻辑单元连接到高速缓存，用于修改存储器设备中的存储器块的原始地址以产生编码的地址。然后使用对编码的地址进行操作的映射函数来定义多个高速缓存一致等级，使得逻辑单元可以用于任意地将给定的一个原始地址分配给高速缓存一致性类别中的特定一个。逻辑单元可以通过设置多个可编程字段来修改原始地址。逻辑单元还可以收集关于高速缓存未命中的信息，并且响应于缓存未命中信息修改原始地址。以这种方式，在处理器上运行的过程并将存储器块分配给高速缓存，使得原始地址（如果应用于映射功能）将导致高速缓存的跨越，则通过使用编码的地址来更有效地运行以导致较少的跨越缓存。

3. 发明授权

US6026470A Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels 失效
标题翻译：软件管理的可编程组合缓存机制监控高速缓存未命中以选择性地实现多个关联级别
公开(公告)号：US6026470A
公开(公告)日：2000-02-15
申请号：US839546
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0864
摘要： A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. Program instructions in the processor select a second associativity level of a known appropriate level, and implement the second associativity level in the cache using a second mapping function. Application software may provide the program instructions, wherein the application software has procedures that may result in cache "strides" at particular associativity levels, and the known appropriate level is chosen to lessen memory latencies due to strides. Alternatively, the program instructions may be part of an operating system which monitors memory address requests, determines how efficient a procedure will operate at different associativity levels, and selects a most efficient level for the known appropriate level. The program instructions may select the associativity level by setting a value in a bit facility corresponding to the desired mapping function.
摘要翻译：公开了一种在由计算机系统的处理器使用的高速缓存中提供可编程关联性的方法。使用第一映射函数来定义存储器块的同余类，从而提供高速缓存的第一组合级别。处理器中的程序指令选择已知适当级别的第二关联级别，并且使用第二映射函数来实现高速缓存中的第二关联级别。应用软件可以提供程序指令，其中应用软件具有可能导致高速缓存在特定关联性级别“大步”的过程，并且选择已知的适当级别以减少由于步幅引起的存储器延迟。或者，程序指令可以是监视存储器地址请求的操作系统的一部分，确定程序在不同的关联级别下的操作有效性，并为已知的适当级别选择最有效的级别。程序指令可以通过设置与期望映射函数相对应的位设施中的值来选择关联性级别。

4. 发明授权

US5978888A Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels 失效
标题翻译：硬件管理的可编程组合缓存机制监控高速缓存未命中，以选择性地实现多个组合级别
公开(公告)号：US5978888A
公开(公告)日：1999-11-02
申请号：US839550
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08
CPC分类号： G06F12/0864
摘要： A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. A logic unit connected to the cache monitors cache misses as the cache uses the first associativity level, and selects other associativity levels based on the cache misses, using other mapping functions. The logic unit has incorporated therein means for selecting the other associativity levels based on a rate of the cache misses in a particular congruence class. The congruence class may be defined by associating the memory block with a particular set of cache blocks in the cache, based on a first portion of an address of the memory block, and the other mapping functions may be implemented by dividing the particular set into subsets and selecting a subset for the memory block based on a second portion of the address.
摘要翻译：公开了一种在由计算机系统的处理器使用的高速缓存中提供可编程关联性的方法。使用第一映射函数来定义存储器块的同余类，从而提供高速缓存的第一组合级别。连接到高速缓存的逻辑单元监视高速缓存未命中，因为高速缓存使用第一关联性级别，并且使用其他映射功能，基于高速缓存未命中选择其他关联性级别。逻辑单元已经结合有用于基于特定同余类中的高速缓存未命中的速率来选择其他关联性级别的装置。可以通过基于存储器块的地址的第一部分将存储器块与高速缓存中的特定的一组高速缓存块相关联来定义同余类，并且可以通过将特定集合划分为子集来实现其他映射函数以及基于所述地址的第二部分来选择所述存储器块的子集。

5. 发明授权

US5974507A Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm 失效
标题翻译：通过选择性地将不同级别的随机性引入替换算法来优化缓存驱逐机制
公开(公告)号：US5974507A
公开(公告)日：1999-10-26
申请号：US837512
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F12/12 , G06F12/02
CPC分类号： G06F12/127 , G06F12/123 , G06F12/0848 , G06F12/0864
摘要： A method of improving operation of a cache used by a processor of a computer system by introducing a level of randomness into a replacement algorithm used by the cache in order to lessen "strides" within the cache is disclosed. Different levels of randomness may be introduced into the replacement algorithm at different times to optimize the cache for different procedures running on the processor. The level of randomness can be selectively introduced by using a basic replacement algorithm to select a subset of a congruence class, and one or more random bits are then used to select a specific cache block within the subset for eviction. The basic replacement algorithm can be a least recently used algorithm. There may be three levels of randomness for a 4-way set associative cache, and there may be four levels of randomness for an 8-way set associative cache.
摘要翻译：公开了一种改进由计算机系统的处理器使用的缓存的操作的方法，其通过将高级别的随机性引入由高速缓存使用的替换算法中以减轻高速缓存内的“跨步”。可以在不同时间将不同级别的随机性引入到替换算法中，以针对在处理器上运行的不同过程优化高速缓存。可以通过使用基本替换算法选择一致等级的子集来选择性地引入随机性的水平，然后使用一个或多个随机比特来选择该子集内的特定高速缓存块进行驱逐。基本替换算法可以是最近最少使用的算法。对于4路组关联缓存，可能存在三个随机性级别，并且对于8路组关联高速缓存可能存在四个级别的随机性。

6. 发明授权

US6058456A Software-managed programmable unified/split caching mechanism for instructions and data 失效
标题翻译：软件管理的可编程统一/分离缓存机制，用于指令和数据
公开(公告)号：US6058456A
公开(公告)日：2000-05-02
申请号：US837515
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/126 , G06F12/0864 , G06F12/0842 , G06F12/0848
摘要： A method of allocating a cache used by a processor of a computer system between instructions and data is disclosed. Program instructions are loaded in the processor for monitoring relative usage of the cache by each value class and selecting a desired ratio of cache usage by the classes from among a plurality of available ratios, and cache blocks within the cache are evicted using a cache-replacement mechanism which restricts replacement of an evicted cache to a particular one of the classes of values (instruction or data) based on the desired ratio of cache usage. A multi-bit facility may be provided to indicate how to confine a selected victim to certain cache blocks, and the program instructions select the desired ratio of cache usage by setting the multi-bit facility. The cache-replacement mechanism can be a modified least recently used replacement mechanism. Different instruction/data ratios thereby may be provided, such as 1:1, 1:2, and 2:1.
摘要翻译：公开了一种在指令和数据之间分配由计算机系统的处理器使用的高速缓存器的方法。程序指令被加载到处理器中，用于监视每个值类的高速缓存的相对使用情况，并从多个可用比率中选择所需类别的高速缓存使用量的期望比率，并且使用高速缓存替换机制，其基于期望的高速缓存使用率限制将逐出缓存的值替换为特定类别的值（指令或数据）。可以提供多位设施来指示如何将选定的受害者限制到某些高速缓存块，并且程序指令通过设置多位设施来选择所需的高速缓存使用率。高速缓存替换机制可以是修改最近最少使用的替换机制。可以提供不同的指令/数据比，例如1：1，2：2和2：1。

7. 发明授权

US06662216B1 Fixed bus tags for SMP buses 失效
标题翻译：用于SMP总线的固定总线标签
公开(公告)号：US06662216B1
公开(公告)日：2003-12-09
申请号：US08839478
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F11/349 , G06F12/0831 , G06F2201/885
摘要： According to a first aspect of the present invention, a data processing system is provided that includes a communication network to which multiple devices are coupled. A first of the multiple devices includes a number of requestors (or queues), which are each permanently assigned a respective one of a number of unique tags. In response to a communication request by a requestor within the first device, a tag assigned to the requestor is transmitted on the communication network in conjunction with the requested communication transaction. According to a second aspect of the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.
摘要翻译：根据本发明的第一方面，提供一种数据处理系统，其包括多个设备耦合到的通信网络。多个设备中的第一个包括多个请求者（或队列），每个请求者（或队列）被永久地分配多个唯一标签中的相应的一个。响应于第一设备内的请求者的通信请求，分配给请求者的标签与所请求的通信事务一起在通信网络上发送。根据本发明的第二方面，数据处理系统包括具有高速缓存目录的高速缓存。指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。响应于接收到高速缓存操作请求，确定是否更新状态指示。响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。状态指示随后被写回缓存目录。因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

8. 发明授权

US06507880B1 Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens 失效
标题翻译：总线协议，总线主机和总线监听器，用于执行使用多个令牌的全局操作
公开(公告)号：US06507880B1
公开(公告)日：2003-01-14
申请号：US09435927
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0831
摘要： In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined token and operation request solicits one of a plurality of tokens required to complete the global operation and identifies the global operation to be processed with the token, if granted. Bus snoopers contain a number of snooper queues for global operations equal to the number of global operation tokens employed within the multiprocessor system. A bus snooper, upon detecting a combined token and operation request, begins speculatively processing the operation if the snooper is not already busy. Before completing the operation, the snooper watches for a combined response with a token number acknowledging either the combined request or a subsequent token request from the same processor, which indicates that the originating bus master has been granted a token for completing a global operation. Otherwise, a combined response acknowledging an operation request containing the token number implies release of the granted token.
摘要翻译：响应于启动全局操作的需要，多处理器系统内的总线主机在耦合到总线主机的总线上发出组合的令牌和操作请求。组合的令牌和操作请求请求完成全局操作所需的多个令牌中的一个令牌，并且如果被授权则标识要用令牌处理的全局操作。总线侦听器包含多个用于全局操作的侦听队列，等于在多处理器系统中使用的全局操作令牌的数量。一旦检测到组合的令牌和操作请求，总线侦听器开始推测性地处理该操作，如果该侦听器尚未忙。在完成操作之前，窥探者使用令牌号来识别来自同一处理器的组合请求或后续令牌请求的组合响应，其指示始发总线主机已经被授予用于完成全局操作的令牌。否则，确认包含令牌号的操作请求的组合响应意味着释放所授予的令牌。

9. 发明授权

US06502171B1 Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data 失效
标题翻译：具有组合侦听响应的多处理器系统总线显式通知窥探者围绕数据
公开(公告)号：US06502171B1
公开(公告)日：2002-12-31
申请号：US09368231
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： In cancelling the cast out portion of a combined operation including a data access related to the cast out, the combined response logic explicitly directs a horizontal storage device at the same level as the storage device initiating the combined operation to allocate and store either the cast out or target data. A horizontal storage device having available space—i.e., an invalid or modified data element in a congruence class for the victim—stores either the target or the cast out data for subsequent access by an intervention. Cancellation of the cast out thus defers any latency associated with writing the cast out victim to system memory while maximizing utilization of available storage with acceptable tradeoffs in data access latency.
摘要翻译：组合响应逻辑在取消组合操作包括与丢弃相关的数据访问的组合操作时，明确指示与启动组合操作的存储设备处于同一级别的水平存储设备，以分配和存储任务或目标数据。具有可用空间的水平存储设备（即，用于受害者的同余类中的无效或修改的数据元素）存储目标或丢弃数据以供随后的干预访问。取消投票，从而延迟与将丢弃的受害者写入系统内存相关的任何延迟，同时最大限度地利用可用存储在数据访问延迟中具有可接受的折中。

10. 发明授权

US06502168B1 Cache having virtual cache controller queues 失效
标题翻译：缓存具有虚拟缓存控制器队列
公开(公告)号：US06502168B1
公开(公告)日：2002-12-31
申请号：US09404028
申请日：1999-09-23
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F11/349 , G06F12/0831 , G06F2201/885
摘要： According to the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.
摘要翻译：根据本发明，数据处理系统包括具有高速缓存目录的高速缓存。指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。响应于接收到高速缓存操作请求，确定是否更新状态指示。响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。状态指示随后被写回缓存目录。因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式