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1. 发明授权

US06505277B1 Method for just-in-time delivery of load data by intervening caches 失效
标题翻译：通过插入缓存来及时传送负载数据的方法
公开(公告)号：US06505277B1
公开(公告)日：2003-01-07
申请号：US09344057
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0806 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F12/0811 , G06F12/0859
摘要： A method for ordering the time of issue of a load instruction from a lower level (L2) intervening cache, interlinked by a system bus to a first L2 cache. The method comprises the steps of (i) appending a cycle of dependency (CoD) value to said load instruction, where the CoD value corresponds to a specified time, measured in cycles, on a synchronized timer (ST) at which the data is required by a downstream dependency, (ii) monitoring when a search of the first cache by said load instruction results in a miss, (iii) searching the load instruction at the second cache when the miss is detected, and (iv) providing the data requested by the load instruction from the intervening cache to a pipeline of a system resource of said first L2 cache at the specified time.
摘要翻译：一种用于从由下一级（L2）中间缓存发出加载指令的时间的方法，该系统总线与第一L2高速缓存相互连接。该方法包括以下步骤：（i）将附加循环（CoD）值附加到所述加载指令，其中CoD值对应于在需要数据的同步定时器（ST）上以周期测量的指定时间通过下游依赖性，（ii）监视当所述加载指令对第一高速缓存的搜索导致错过时，（iii）在检测到未命中时搜索第二高速缓存上的加载指令，以及（iv）提供所请求的数据通过在指定时间从中间缓存到所述第一L2高速缓存的系统资源的流水线的加载指令。

2. 发明授权

US06581139B1 Set-associative cache memory having asymmetric latency among sets 有权
标题翻译：集合中具有不对称延迟的集合关联高速缓存存储器
公开(公告)号：US06581139B1
公开(公告)日：2003-06-17
申请号：US09339411
申请日：1999-06-24
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0864
摘要： A set-associative cache memory having asymmetric latency among sets is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets organized in a set-associative manner. The cache memory further includes a means for accessing at least one of the sets faster than the remaining sets having an identical access latency.
摘要翻译：公开了一组在集合中具有非对称等待时间的组合高速缓冲存储器。高速缓存存储器具有多个一致的缓存行类。每个同余类包括以组合方式组织的多个集合。高速缓冲存储器还包括用于比具有相同访问延迟的其余集合更快地访问集合中的至少一个集合的装置。

3. 发明授权

US06510494B1 Time based mechanism for cached speculative data deallocation 失效
标题翻译：缓存的推测数据释放的基于时间的机制
公开(公告)号：US06510494B1
公开(公告)日：2003-01-21
申请号：US09345716
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
IPC分类号： G06F1208
CPC分类号： G06F9/3802 , G06F9/383 , G06F12/0862 , G06F12/0897
摘要： A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the pref etch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit.
摘要翻译：一种操作计算机系统的处理单元的方法，通过从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。本发明适用于作为操作数数据或指令的值。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用pref蚀刻请求发送将预取值加载到处理单元的较低级缓存中的指示。本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联。

4. 发明授权

US06460118B1 Set-associative cache memory having incremental access latencies among sets 失效
标题翻译：集合中具有增量访问延迟的集合关联缓存存储器
公开(公告)号：US06460118B1
公开(公告)日：2002-10-01
申请号：US09339410
申请日：1999-06-24
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： C06F1200
CPC分类号： G06F12/0864 , G06F12/1054
摘要： A set-associative cache memory having incremental access latencies among sets is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets organized in a set-associative manner. In accordance with a preferred embodiment of the present invention, the cache memory further includes a means for accessing each of the sets with an access time dependent on a relative location of each of the sets such that access latency varies incrementally among sets.
摘要翻译：公开了一种在集合中具有增量接入延迟的集合关联高速缓冲存储器。高速缓存存储器具有多个一致的缓存行类。每个同余类包括以组合方式组织的多个集合。根据本发明的优选实施例，高速缓存存储器还包括用于以取决于每个集合的相对位置的访问时间来访问每个集合的装置，使得访问延迟在集合之间递增地变化。

5. 发明授权

US06460117B1 Set-associative cache memory having a mechanism for migrating a most recently used set 失效
标题翻译：具有用于迁移最近使用的集合的机制的集合关联缓存存储器
公开(公告)号：US06460117B1
公开(公告)日：2002-10-01
申请号：US09339409
申请日：1999-06-24
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0893 , G06F12/0864 , G06F12/123
摘要： A set-associative cache memory having a mechanism for migrating a most recently used set is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets organized in a set-associative manner. The cache memory further includes a migration means for directing the information from a cache “hit” to a predetermined set of the cache memory.
摘要翻译：公开了具有用于迁移最近使用的集合的机制的集合关联缓存存储器。高速缓存存储器具有多个一致的缓存行类。每个同余类包括以组合方式组织的多个集合。高速缓冲存储器还包括用于将信息从高速缓存“命中”引导到高速缓冲存储器的预定集合的迁移装置。

6. 发明授权

US06421763B1 Method for instruction extensions for a tightly coupled speculative request unit 有权
标题翻译：紧耦合推测请求单元的指令扩展方法
公开(公告)号：US06421763B1
公开(公告)日：2002-07-16
申请号：US09345642
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
IPC分类号： G06F1208
CPC分类号： G06F12/0862 , G06F9/3802 , G06F9/383 , G06F9/3885 , G06F12/0897 , G06F2212/6028
摘要： A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hierarchy, and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value. The prefetch limit of cache usage may be established with a maximum number of sets in a congruence class usable by the requesting processing unit. A flag in a directory of the cache may be set to indicate that the prefetch value was retrieved as the result of a prefetch operation. In the implementation wherein the cache is a multi-level cache, a second flag in the cache directory may be set to indicate that the prefetch value has been sourced to an upstream cache. A cache line containing prefetch data can be automatically invalidated after a preset amount of time has passed since the prefetch value was requested.
摘要翻译：一种操作计算机系统的处理单元的方法，通过从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。本发明适用于作为操作数数据或指令的值。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。如果从存储器层次结构请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已经被高速缓存满足，则分配包含较早预取值之一的高速缓存行中的高速缓存行用于接收另一个预取值。高速缓存使用的预取限制可以由请求处理单元可用的同余类中的最大数量的集合来建立。高速缓存目录中的标志可以被设置为指示作为预取操作的结果检索预取值。在其中缓存是多级高速缓存的实现中，高速缓存目录中的第二标志可以被设置为指示预取值已经被提供给上游高速缓存。包含预取数据的缓存行可以在从请求预取值开始经过预设的时间后自动失效。

7. 发明授权

US06385702B1 High performance multiprocessor system with exclusive-deallocate cache state 失效
标题翻译：具有独占解除缓存状态的高性能多处理器系统
公开(公告)号：US06385702B1
公开(公告)日：2002-05-07
申请号：US09437198
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A cache coherency protocol uses a “Exclusive-Deallocate” (ED) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form (not shared with any other caches of the computer system, including caches associated with the same processing unit), so that the value can conveniently be modified without any lower level bus transactions since no lower level caches have allocated a line for the value. If the value is subsequently modified in the upper level cache, its coherency state is simply switched to “modified” without the need for any bus transactions. Conversely, if the value is evicted from the upper level cache without ever having been modified, it can be loaded into the lower level cache with a coherency state indicating that the lower level cache contains the unmodified value exclusive of all other caches in other processing units of the computer system. If the value is initially loaded into the upper level cache from a cache of another processing unit, or from a lower level cache of the same processing unit, then the upper level cache may be selectively programmed to mark the cache line with the ED state.
摘要翻译：高速缓存一致性协议使用“独占解除分配”（ED）一致性状态来指示特定值当前以独占未修改的形式（不与计算机系统的任何其他高速缓存共享，包括高速缓存）保持在高级缓存中与相同的处理单元关联），使得该值可以方便地被修改而没有任何较低级别的总线事务，因为没有较低级别的高速缓存已经为该值分配了一行。如果该值随后在高级缓存中被修改，则其一致性状态被简单地切换到“修改”，而不需要任何总线事务。相反，如果该值从上级缓存中被逐出而没有被修改，则可以将其加载到具有一致性状态的相关性状态中，该相关性状态指示低级缓存包含其他处理单元中所有其他高速缓存的排他性的未修改值的计算机系统。如果该值最初从另一处理单元的高速缓存或相同处理单元的较低级高速缓存加载到高级缓存中，则可以选择性地编程高级缓存以用ED状态标记高速缓存行。

8. 发明授权

US06629214B1 Extended cache coherency protocol with a persistent “lock acquired” state 失效
标题翻译：具有持续“锁获取”状态的扩展缓存一致性协议
公开(公告)号：US06629214B1
公开(公告)日：2003-09-30
申请号：US09437186
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1300
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3857
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized. In particular, the claimed system and method provides that a given processor, after acquiring a lock or reservation to a given cache line, will keep the lock, to make successive modifications to the cache line, instead of releasing it to other processors after making only one modification. By doing so, the overhead typically required to acquire a lock before making any cache line modification is eliminated for successive modifications.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的传统系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。额外的缓存状态允许优化缓存状态转换序列。特别地，所要求保护的系统和方法规定，给定的处理器在获得对给定高速缓存行的锁定或预留之后将保持锁定以对缓存行进行连续修改，而不是在仅进行制作之后将其释放到其他处理器一个修改。通过这样做，为了连续修改，消除了在进行任何高速缓存行修改之前获取锁的通常需要的开销。

9. 发明授权

US06393528B1 Optimized cache allocation algorithm for multiple speculative requests 失效
标题翻译：针对多个推测请求的优化缓存分配算法
公开(公告)号：US06393528B1
公开(公告)日：2002-05-21
申请号：US09345714
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/127
摘要： A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hiearchy and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value.
摘要翻译：公开了一种操作计算机系统的方法，其中具有显式预取请求的指令直接从指令序列单元发送到处理单元的预取单元。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。如果从存储器hiearchy请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已被满足，则包含先前预取值中的一个的高速缓存行中的高速缓存行被分配用于接收另一个预取值。

10. 发明授权

US06345344B1 Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits 失效
标题翻译：修改未经请求的缓存状态的缓存分配机制，修改受害优先级位
公开(公告)号：US06345344B1
公开(公告)日：2002-02-05
申请号：US09437181
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/126 , G06F12/0831
摘要： A novel cache coherency protocol provides a modified-unsolicited (Mu) cache state to indicate that a value held in 5 a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the Mu state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The Mu state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the Mu state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
摘要翻译：一种新颖的高速缓存一致性协议提供修改后的未经请求（Mu）高速缓存状态，以指示缓存行5中保存的值已经被修改（即当前与系统存储器不一致），但是被另一个处理单元修改通过与当前包含Mu状态的值的高速缓存相关联的处理单元，并且该值被保持为排除任何其他水平相邻的高速缓存。因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。作为对读取请求的窥探响应的结果，可以应用Mu状态。读取请求可以包括用于指示请求的高速缓存能够利用Mu状态的标志。或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

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