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1. 发明授权

US4122493A Adaptive wideband AFC system 失效
标题翻译：自适应宽带AFC系统
公开(公告)号：US4122493A
公开(公告)日：1978-10-24
申请号：US833759
申请日：1977-09-16
申请人： Rangaswamy Arumugham , George Hager Kam
发明人： Rangaswamy Arumugham , George Hager Kam
IPC分类号： H03J7/10 , H04N5/50 , H04B1/16
CPC分类号： H03J7/10 , H04N5/50
摘要： Circuitry compensating for inherent nonlinearities in the tuning voltage sensitivity of varactor tuners, thereby providing relatively constant AFC pull-in range throughout the band of operating frequencies, is shown. In both the VHF and UHF bands, the AFC system develops an error correction voltage in proportion to the tuning voltage. With respect to reception of VHF channels, a gain switching circuit operates to reduce the proportion of AFC error correction voltage developed on a High Band VHF channel, thereby compensating for increased tuning voltage sensitivity on High Band VHF. With respect to reception of UHF channels, a tuning voltage sensing circuit operates to effect an error correction voltage that is a greater proportion of the tuning voltage when the tuning voltage is above a pre-determined value corresponding to approximately channel 60.
摘要翻译：示出了补偿变容二极管调谐器的调谐电压灵敏度中的固有非线性的电路，从而在整个工作频率带提供相对恒定的AFC拉入范围。在VHF和UHF频段中，AFC系统与调谐电压成比例地产生纠错电压。关于VHF信道的接收，增益切换电路用于降低在高频带VHF信道上产生的AFC误差校正电压的比例，从而补偿在高频带VHF上提高的调谐电压灵敏度。关于UHF通道的接收，调谐电压感测电路操作以实现当调谐电压高于对应于大约通道60的预定值时调谐电压的较大比例的纠错电压。

2. 发明申请

US20080256379A1 Clock architecture for multi-processor systems 有权
标题翻译：多处理器系统的时钟架构
公开(公告)号：US20080256379A1
公开(公告)日：2008-10-16
申请号：US11786125
申请日：2007-04-11
申请人： Rangaswamy Arumugham , Mark Shaw , Russ W. Herrell , Lisa Pallotti
发明人： Rangaswamy Arumugham , Mark Shaw , Russ W. Herrell , Lisa Pallotti
IPC分类号： G06F1/06
CPC分类号： G06F1/10
摘要： In one embodiment, a computer system, comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, a routing device to couple the first and second computing cells, a global clock signal source coupled to the at least two computing cells to generate a global clock signal, at least one timing manager to generate a timing control signal, wherein the at least two computing cells comprise a local oscillator to generate a local clock signal, and a multiplexer coupled to receive the global clock signal, the local clock signal, and the timing control signal, and to output one of the global clock signal or the local clock signal in response to the control signal.
摘要翻译：在一个实施例中，计算机系统至少包括第一计算单元和第二计算单元，每个计算单元包括至少一个处理器，耦合第一和第二计算单元的路由设备，耦合到第一计算单元的全局时钟信号源至少两个计算单元以产生全局时钟信号，至少一个定时管理器产生定时控制信号，其中所述至少两个计算单元包括本地振荡器以产生本地时钟信号，以及多路复用器，用于接收全局时钟信号时钟信号，本地时钟信号和定时控制信号，并且响应于控制信号输出全局时钟信号或本地时钟信号之一。

3. 发明申请

US20080080566A1 System and method for distributing clock signals 有权
标题翻译：用于分配时钟信号的系统和方法
公开(公告)号：US20080080566A1
公开(公告)日：2008-04-03
申请号：US11540244
申请日：2006-09-29
申请人： Rangaswamy Arumugham , Lisa Pallotti
发明人： Rangaswamy Arumugham , Lisa Pallotti
IPC分类号： H04J3/06
CPC分类号： G06F1/12
摘要： There is provided a method of operating a computer system. The computer system comprises at least two cabinets and the at least two cabinets have at least one clock signal. The method includes selecting one of the at least one clock signal to serve as a master signal, and synchronizing the computer system to operate from the master signal. Additionally, the method includes altering the capacity of the system while the system is operating.
摘要翻译：提供了一种操作计算机系统的方法。所述计算机系统包括至少两个机柜，并且所述至少两个机柜具有至少一个时钟信号。该方法包括选择至少一个时钟信号中的一个作为主信号，并使计算机系统与主信号同步工作。此外，该方法包括在系统运行时改变系统的容量。

4. 发明授权

US07809025B2 System and method for distributing clock signals 有权
标题翻译：用于分配时钟信号的系统和方法
公开(公告)号：US07809025B2
公开(公告)日：2010-10-05
申请号：US11540244
申请日：2006-09-29
申请人： Rangaswamy Arumugham , Lisa Pallotti
发明人： Rangaswamy Arumugham , Lisa Pallotti
IPC分类号： H04J3/06
CPC分类号： G06F1/12
摘要： There is provided a method of operating a computer system. The computer system comprises at least two cabinets and the at least two cabinets have at least one clock signal. The method includes selecting one of the at least one clock signal to serve as a master signal, and synchronizing the computer system to operate from the master signal. Additionally, the method includes altering the capacity of the system while the system is operating.
摘要翻译：提供了一种操作计算机系统的方法。所述计算机系统包括至少两个机柜，并且所述至少两个机柜具有至少一个时钟信号。该方法包括选择至少一个时钟信号中的一个作为主信号，并使计算机系统与主信号同步工作。此外，该方法包括在系统运行时改变系统的容量。

5. 发明授权

US4290005A Compensated reference voltage source 失效
标题翻译：补偿参考电压源
公开(公告)号：US4290005A
公开(公告)日：1981-09-15
申请号：US166526
申请日：1980-07-07
申请人： Rangaswamy Arumugham
发明人： Rangaswamy Arumugham
IPC分类号： G05F3/18 , G05F3/30 , G05F3/20
CPC分类号： G05F3/18 , G05F3/30
摘要： A compensated reference voltage source for providing a stable output voltage despite variations in operating voltage. The circuitry includes a series arrangement of a first resistance, a Zener diode, and a second resistance connected between a source of operating voltage and ground. A first transistor has its collector connected to the juncture of the first resistance and the Zener diode, its base connected to the juncture of the Zener diode and the second resistance, and its emitter connected to ground. A second transistor has its base and emitter connected directly to the corresponding electrodes of the first transistor and its collector connected to an output terminal. A third transistor has its collector connected to the source of operating voltage, its emitter connected to the output terminal, and its base connected to the collector of the first transistor. The base-emitter characteristics of the transistors are essentially identical. The voltage across the Zener diode remains constant despite variations in the operating voltage. However, the voltage at the collector of the first transistor varies because of changes in current flow across its base-emitter junction. Because of the interconnections, equal currents flow through each of the transistors. Since the base-emitter characteristics of the transistors are identical, the voltage drops across the base-emitter junctions of the first and third transistors are equal. Thus, the voltage at the output terminal is equal to the voltage across the Zener diode and remains constant despite variations in the operating voltage.
摘要翻译：补偿参考电压源，尽管工作电压有变化，但仍可提供稳定的输出电压。电路包括串联的第一电阻，齐纳二极管和连接在工作电压源和地之间的第二电阻。第一晶体管的集电极连接到第一电阻和齐纳二极管的接合点，其基极连接到齐纳二极管和第二电阻的接合端，其发射极连接到地。第二晶体管的基极和发射极直接连接到第一晶体管的相应电极，其集电极连接到输出端。第三晶体管的集电极连接到工作电压源，其发射极连接到输出端，其基极连接到第一晶体管的集电极。晶体管的基极 - 发射极特性基本相同。尽管工作电压有变化，齐纳二极管两端的电压保持不变。然而，第一晶体管的集电极处的电压由于其基极 - 发射极结上的电流的变化而变化。由于互连，相等的电流流过每个晶体管。由于晶体管的基极 - 发射极特性相同，所以第一和第三晶体管的基极 - 发射极结两端的电压相等。因此，输出端子处的电压等于齐纳二极管两端的电压，尽管工作电压有变化，但仍保持恒定。

6. 发明授权

US07814301B2 Clock architecture for multi-processor systems 有权
标题翻译：多处理器系统的时钟架构
公开(公告)号：US07814301B2
公开(公告)日：2010-10-12
申请号：US11786125
申请日：2007-04-11
申请人： Rangaswamy Arumugham , Mark Shaw , Russ W. Herrell , Lisa Pallotti
发明人： Rangaswamy Arumugham , Mark Shaw , Russ W. Herrell , Lisa Pallotti
IPC分类号： G06F9/00
CPC分类号： G06F1/10
摘要： In one embodiment, a computer system, comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, a routing device to couple the first and second computing cells, a global clock signal source coupled to the at least two computing cells to generate a global clock signal, at least one timing manager to generate a timing control signal, wherein the at least two computing cells comprise a local oscillator to generate a local clock signal, and a multiplexer coupled to receive the global clock signal, the local clock signal, and the timing control signal, and to output one of the global clock signal or the local clock signal in response to the control signal.
摘要翻译：在一个实施例中，计算机系统至少包括第一计算单元和第二计算单元，每个计算单元包括至少一个处理器，耦合第一和第二计算单元的路由设备，耦合到第一计算单元的全局时钟信号源至少两个计算单元以产生全局时钟信号，至少一个定时管理器产生定时控制信号，其中所述至少两个计算单元包括本地振荡器以产生本地时钟信号，以及多路复用器，用于接收全局时钟信号时钟信号，本地时钟信号和定时控制信号，并且响应于控制信号输出全局时钟信号或本地时钟信号之一。

7. 发明授权

US4005256A AFC circuit 失效
标题翻译： AFC电路
公开(公告)号：US4005256A
公开(公告)日：1977-01-25
申请号：US628072
申请日：1975-11-03
申请人： Rangaswamy Arumugham
发明人： Rangaswamy Arumugham
IPC分类号： H03J7/10 , H04B1/16
CPC分类号： H03J7/10
摘要： A signal combining circuit for combining a tuning bias voltage and an automatic frequency control error voltage for application to a voltage controlled radio frequency tuning means for a television receiver is shown. The voltage controlled radio frequency tuning means has a non-linear frequency versus voltage characteristic and the signal combining circuit includes a resistance means for coupling the error voltage to the tuning means input in a manner that compensates for the non-linearity of the frequency versus voltage characteristic of the tuning means to provide a substantially constant automatic frequency control pull-in range throughout the frequency range of interest.
摘要翻译：示出了用于组合调谐偏置电压和自动频率控制误差电压的信号组合电路，用于电视接收机的压控射频调谐装置。压控射频调谐装置具有非线性的频率对电压特性，信号组合电路包括用于以补偿频率对电压的非线性的方式将误差电压耦合到调谐装置输入的电阻装置该调谐装置的特征在于在感兴趣的整个频率范围内提供基本恒定的自动频率控制拉入范围。

8. 发明授权

US3944725A Wide band automatic frequency control circuit 失效
标题翻译：宽带自动频率控制电路
公开(公告)号：US3944725A
公开(公告)日：1976-03-16
申请号：US554316
申请日：1975-02-28
申请人： Rangaswamy Arumugham , William Frank Kruszewski , Karol Siwko
发明人： Rangaswamy Arumugham , William Frank Kruszewski , Karol Siwko
IPC分类号： H03J7/04 , H04N5/50 , H04N7/06
CPC分类号： H03J7/04 , H04N5/50
摘要： An automatic frequency control (AFC) circuit for a signal receiver having a tuner, intermediate frequency (IF) amplifier, video amplifier, and sync pulse separation means includes a discriminator coupled to the IF stage and a signal combining means coupled to the discriminator means and sync pulse separation means and to the tuner to effect a given "pull-in" range for the tuner in response to error signals from the discriminator and an increased "pull-in" range upon loss of sync signals from the sync pulse separation means when the tuner stage is increasingly detuned.
摘要翻译：用于具有调谐器，中频（IF）放大器，视频放大器和同步脉冲分离装置的信号接收机的自动频率控制（AFC）电路包括耦合到IF级的鉴频器和耦合到鉴频器装置的信号组合装置，同步脉冲分离装置和调谐器，以响应于来自鉴别器的误差信号而对调谐器施加给定的“拉入”范围，并且当从同步脉冲分离装置丢失同步信号时增加“拉入”范围，调谐器阶段越来越失败。

9. 发明授权

US4245236A Chrominance take-off circuit 失效
标题翻译：色度起飞电路
公开(公告)号：US4245236A
公开(公告)日：1981-01-13
申请号：US950500
申请日：1978-10-11
申请人： Rangaswamy Arumugham
发明人： Rangaswamy Arumugham
IPC分类号： H04N9/78 , H04N9/535
CPC分类号： H04N9/78
摘要： A chrominance take-off circuit effecting a transmission zero at a predetermined frequency approximately equal to one-half the chrominance subcarrier frequency. The circuit includes a capacitive branch coupled in series with a parallel RLC branch that is resonant at approximately the subcarrier frequency. At frequencies below the subcarrier frequency the RLC branch is equivalent to a series-connected resistance and inductance. At the predetermined frequency the magnitude of the impedance of the capacitive branch is substantially equal to the magnitude of the impedance of the equivalent inductance, resulting in maximum attenuation of luminance signals at the predetermined frequency.
摘要翻译：色度输出电路以大致等于色度副载波频率的一半的预定频率实现传输零点。电路包括与并联RLC分支串联耦合的电容分支，其大约在子载波频率处共振。在低于子载波频率的频率下，RLC分支等效于串联电阻和电感。在预定频率下，电容性分支的阻抗的大小基本上等于等效电感的阻抗的大小，导致在预定频率下的亮度信号的最大衰减。

10. 发明授权

US4153914A Network for applying a plurality of control voltages to a common control terminal 失效
标题翻译：用于将多个控制电压施加到公共控制终端的网络
公开(公告)号：US4153914A
公开(公告)日：1979-05-08
申请号：US892118
申请日：1978-03-31
申请人： Rangaswamy Arumugham , George H. Kam
发明人： Rangaswamy Arumugham , George H. Kam
IPC分类号： H03J7/12 , H04N5/50 , H03K5/00 , H04B1/16
CPC分类号： H03J7/12
摘要： A network for combining a switchable and variable tuning voltage with an AFC voltage so as to effect a change in the tuning control voltage at a tuner's tuning control terminal is disclosed. The network compensates for time delays associated with the AFC time-constant in a manner such that the tuning control voltage responds in proportion to and substantially instantaneously with changes in the tuning voltage. The compensation reduces the probability of AFC false-locking phenomena when, for example, switching from one channel of a television receiver to another.
摘要翻译：公开了一种用于将可切换和可变调谐电压与AFC电压组合以便在调谐器调谐控制端子处实现调谐控制电压变化的网络。网络补偿与AFC时间常数相关的时间延迟，使得调谐控制电压与调谐电压的变化成比例地且基本上瞬时地响应。当例如从电视接收机的一个频道切换到另一个频道时，该补偿降低了AFC假锁定现象的可能性。

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