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1. 发明授权

US06192459B1 Method and apparatus for retrieving data from a data storage device 失效
公开(公告)号：US06192459B1
公开(公告)日：2001-02-20
申请号：US09046941
申请日：1998-03-23
申请人： Randy M. Bonella , Peter D. MacWilliams , Konrad K. Lai
发明人： Randy M. Bonella , Peter D. MacWilliams , Konrad K. Lai
IPC分类号： G00F1200
CPC分类号： G06F12/0864 , G06F12/0879
摘要： A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.

2. 发明授权

US06397291B2 Method and apparatus for retrieving data from a data storage device 有权
标题翻译：从数据存储装置检索数据的方法和装置
公开(公告)号：US06397291B2
公开(公告)日：2002-05-28
申请号：US09730876
申请日：2000-12-05
申请人： Randy M. Bonella , Peter D. MacWilliams , Konrad K. Lai
发明人： Randy M. Bonella , Peter D. MacWilliams , Konrad K. Lai
IPC分类号： G06F1200
CPC分类号： G06F12/0864 , G06F12/0879
摘要： A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.
摘要翻译：数据检索系统接收识别要检索的数据的数据地址。接收的数据地址的一部分在第一时钟周期期间传送到数据存储设备。该系统基于接收的数据地址确定第二地址部分。第二地址部分在第二时钟周期期间传送到数据存储设备。然后基于传送到数据存储装置的地址部分从数据存储装置检索数据。在第一时钟周期期间传送到数据存储设备的接收数据地址的部分是设置地址，并且在第二时钟周期期间传送到数据存储设备的第二地址部分是一种地址。在第一时钟周期期间将接收的数据地址的一部分传送到数据存储设备之后，可以启动读周期。

3. 再颁专利

USRE38388E1 Method and apparatus for performing deferred transactions 有权
标题翻译：执行延期交易的方法和装置
公开(公告)号：USRE38388E1
公开(公告)日：2004-01-13
申请号：US09882444
申请日：2001-06-14
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
IPC分类号： H04L12417
CPC分类号： G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

4. 发明授权

US5615343A Method and apparatus for performing deferred transactions 失效
标题翻译：执行延期交易的方法和装置
公开(公告)号：US5615343A
公开(公告)日：1997-03-25
申请号：US302600
申请日：1994-09-08
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams , Stephen S. Pawlowski , Michael W. Rhodehamel
IPC分类号： G06F13/36 , G06F13/368 , G06F13/37 , G06F13/42
CPC分类号： G06F13/37 , G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：在计算机系统的总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

5. 发明授权

US5937171A Method and apparatus for performing deferred transactions 失效
标题翻译：执行延期交易的方法和装置
公开(公告)号：US5937171A
公开(公告)日：1999-08-10
申请号：US669101
申请日：1996-06-26
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams
IPC分类号： G06F13/36 , G06F13/368 , G06F13/37 , G06F13/42 , H04L12/417 , G06F13/14
CPC分类号： G06F13/37 , G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：在计算机系统的总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

6. 发明申请

US20160239304A1 METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE ABORT CONTROL MECHANISMS 审中-公开
标题翻译：用于结构控制机制的方法，装置和系统
公开(公告)号：US20160239304A1
公开(公告)日：2016-08-18
申请号：US14757857
申请日：2015-12-26
申请人： Martin G. Dixon , Ravi Rajwar , Konrad K. Lai , Robert S. Chappell , Rajesh S. Parthasarathy , Alexandre J. Farcy , Ilhyun Kim , Prakash Math , Matthew Merten , Vijaykumar Kadgi
发明人： Martin G. Dixon , Ravi Rajwar , Konrad K. Lai , Robert S. Chappell , Rajesh S. Parthasarathy , Alexandre J. Farcy , Ilhyun Kim , Prakash Math , Matthew Merten , Vijaykumar Kadgi
IPC分类号： G06F9/38 , G06F9/30 , G06F12/08 , G06F12/10 , G06F9/46
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/3859 , G06F9/3861 , G06F9/467 , G06F9/528 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0895 , G06F12/0897 , G06F12/1027 , G06F12/1045 , G06F13/1673 , G06F13/4068 , G06F13/4282 , G06F2212/452 , G06F2212/50 , G06F2212/60 , G06F2212/602 , G06F2212/621 , G06F2212/68 , G06F2212/682
摘要： An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.
摘要翻译：本文描述了一种用于提供鲁棒的推测代码部分中止控制机制的装置和方法。硬件能够跟踪推测性代码区域中止事件，条件和/或场景，例如显式中止指令，数据冲突，推测定时器到期，不允许的指令属性或类型等。硬件，固件，软件，或其组合基于跟踪的中止事件进行中止判定。作为示例，硬件可以基于一个或多个预定义事件进行初始中止确定，或者选择将事件信息传递到固件或软件处理程序以进行这种中止确定。在确定要执行推测代码区域的中止时，硬件，固件，软件或其组合执行中止，其可以包括跟随由硬件或软件指定的回退路径。并且为了能够测试这样的回退路径，在一个实现中，硬件为软件提供一种总是中止推测代码区域的机制。

7. 发明申请

US20150032998A1 METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS 审中-公开
标题翻译：方法，装置和系统的交互式分析控制指令
公开(公告)号：US20150032998A1
公开(公告)日：2015-01-29
申请号：US13997243
申请日：2012-02-02
申请人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Alexandre J. Farcy , Bret L. Toll , Robert S. Chappell , Matthew C. Merten , Rajesh S. Parthasarathy , Per Hammarlund
发明人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Alexandre J. Farcy , Bret L. Toll , Robert S. Chappell , Matthew C. Merten , Rajesh S. Parthasarathy , Per Hammarlund
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3004 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F9/3851 , G06F9/3859
摘要： An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similarly provided for in an Instruction Set Architecture (ISA) to define a transactional code region. In addition, other control speculation instructions, such as xAbort to enable explicit abort of a critical or transactional code section and xTest to test a state of speculative execution is also provided in the ISA.
摘要翻译：这里描述了一种用于提供猜测控制指令的装置和方法。提供xAcquire和xRelease指令来定义关键部分。在一个实施例中，xAcquire指令包括具有检验前缀的锁定指令，并且xRelease指令包括具有检验前缀的锁定释放指令。因此，处理器能够通过xAcquire和xRelease来删除锁定和事务性地执行在软件中定义的关键部分。但是通过仅添加前缀提示，传统处理器能够通过忽略提示并执行传统的锁定关键部分来保证互斥，从而执行相同的代码。此外，xBegin和xEnd在指令集架构（ISA）中类似地提供以定义事务代码区域。此外，还在ISA中提供了其他控制推测指令，例如xAbort，以实现关键或事务代码段的显示中止，以及xTest测试推测执行状态。

8. 发明授权

US5903738A Method and apparatus for performing bus transactions in a computer system 失效
标题翻译：用于在计算机系统中执行总线事务的方法和装置
公开(公告)号：US5903738A
公开(公告)日：1999-05-11
申请号：US715049
申请日：1996-09-17
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh
IPC分类号： G06F13/368 , G06F13/37 , G06F13/42 , G06F3/00
CPC分类号： G06F13/4213 , G06F13/368 , G06F13/37
摘要： A method and apparatus of performing bus transactions on the external bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：一种在计算机系统的外部总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

9. 发明授权

US5617554A Physical address size selection and page size selection in an address translator 失效
标题翻译：地址翻译器中的物理地址大小选择和页面大小选择
公开(公告)号：US5617554A
公开(公告)日：1997-04-01
申请号：US372805
申请日：1994-12-23
申请人： Donald B. Alpert , Kenneth D. Shoemaker , Kevin C. Kahn , Konrad K. Lai
发明人： Donald B. Alpert , Kenneth D. Shoemaker , Kevin C. Kahn , Konrad K. Lai
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F2212/652
摘要： An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size. For a large memory size, the tables include a directory pointer table that includes a group of directory pointers, a plurality of page table directories each of which includes a group of page directory entries, and a plurality of page tables each of which includes a group of page table entries. The size of the entries in the tables is dependent upon the selected memory size. The contents of the tables are stored in memory, and furthermore the pointer table is stored in both main memory and in dedicated pointer table registers.
摘要翻译：这里描述了地址转换器和用于将线性地址翻译成用于计算机中的存储器管理的物理地址的方法。可以选择不同的内存大小和不同的页面大小。地址转换器可以从标准的32位线性地址转换，以兼容以前的32位体系结构，并且还可以转换为具有比线性地址更大的物理地址的物理内存大小; 即大于32位（例如36位及以上），而不增加访问时间。地址转换器翻译包括用于选择多个表中的条目的偏移和多个字段的线性地址。线性地址到字段的格式取决于所选的内存大小和所选的页面大小。对于大的存储器大小，表包括目录指针表，其包括一组目录指针，多个页表目录，每个页表目录包括一组页目录条目，以及多个页表，每个页表包括一组的页表条目。表中条目的大小取决于所选的内存大小。表的内容存储在存储器中，此外，指针表存储在主存储器和专用指针表寄存器中。

10. 发明授权

US5550988A Apparatus and method for performing error correction in a multi-processor system 失效
标题翻译：用于在多处理器系统中执行纠错的装置和方法
公开(公告)号：US5550988A
公开(公告)日：1996-08-27
申请号：US205604
申请日：1994-03-01
申请人： Nitin V. Sarangdhar , Konrad K. Lai
发明人： Nitin V. Sarangdhar , Konrad K. Lai
IPC分类号： G06F11/14 , G06F13/36
CPC分类号： G06F13/36 , G06F11/1402
摘要： In a multi-processor system having a first processor, a second processor, and a bus coupling the first processor to the second processor, a method for correcting an erroneous signal corresponding to the first processor while maintaining lock atomicity. When an erroneous transaction is detected, the first processor aborts that transaction and performs a retry. On the retry, an arbitration process arbitrates between the first processor and the second processor to determine which processor is granted access to the bus. If an error is detected during the arbitration process, an arbitration re-synchronization process is initiated. In the arbitration re-synchronization process, bus requests are de-asserted and then re-arbitrated. In the re-arbitration process, the first processor initiates its request ahead of the other processor in order to maintain lock atomicity.
摘要翻译：在具有第一处理器，第二处理器和将第一处理器耦合到第二处理器的总线的多处理器系统中，一种用于在保持锁原子性的同时校正与第一处理器相对应的错误信号的方法。当检测到错误的事务时，第一处理器中止该事务并执行重试。在重试时，仲裁过程在第一处理器和第二处理器之间进行仲裁以确定哪个处理器被授权访问总线。如果在仲裁过程中检测到错误，则启动仲裁重新同步过程。在仲裁重新同步过程中，总线请求被取消断言，然后重新仲裁。在重新仲裁过程中，第一个处理器在另一个处理器之前发起其请求，以保持锁定原子性。

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