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1. 发明授权

US06414376B1 Method and apparatus for reducing isolation stress in integrated circuits 失效
标题翻译：降低集成电路隔离应力的方法和装置
公开(公告)号：US06414376B1
公开(公告)日：2002-07-02
申请号：US09252837
申请日：1999-02-19
申请人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
发明人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
IPC分类号： H01L2358
CPC分类号： H01L21/32 , H01L21/0332
摘要： Stress resulting from silicon nitride is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride by varying the amount of hydride, such as dichlorosilane (DCS), mixed with ammonia. The silicon nitride can be graded in a substantially linear or non-linear fashion. Silicon nitride formed with higher levels of DCS mixed with ammonia is referred to as silicon rich nitride because of its relatively higher silicon content. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress from the silicon nitride is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, the stress from the silicon nitride is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.
摘要翻译：通过用具有梯度硅浓度的氮化硅形成氧化掩模来减小氮化硅产生的应力。通过改变与氨混合的氢化物（例如二氯硅烷（DCS））的量来改变氮化硅中的硅含量来实现分级。氮化硅可以以基本线性或非线性方式分级。由于硅含量相对较高，因此与氨混合的较高水平的DCS形成的氮化硅被称为富含氮的氮化物。在一个实施例中，渐变氮化硅可以用一种类型的非线性硅分级，突变结形成。在其它实施例中，氮化硅形成为在氮化硅生长期间或之后形成的各种形状。在一个实施例中，通过在两个氮化硅层之间形成多晶硅缓冲层来减小来自氮化硅的应力。在另一个实施方案中，通过在衬底层上形成氮化硅来降低来自氮化硅的应力，衬垫层又形成在基底层上。

2. 发明授权

US6051511A Method and apparatus for reducing isolation stress in integrated circuits 失效
公开(公告)号：US6051511A
公开(公告)日：2000-04-18
申请号：US904054
申请日：1997-07-31
申请人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
发明人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
IPC分类号： H01L21/033 , H01L21/32 , H01L21/31 , H01L21/469
CPC分类号： H01L21/32 , H01L21/0332
摘要： Stress resulting from silicon nitride is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride by varying the amount of hydride, such as dichlorosilane (DCS), mixed with ammonia. The silicon nitride can be graded in a substantially linear or non-linear fashion. Silicon nitride formed with higher levels of DCS mixed with ammonia is referred to as silicon rich nitride because of its relatively higher silicon content. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress from the silicon nitride is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, the stress from the silicon nitride is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.

3. 发明授权

US06602798B1 Method and apparatus for reducing isolation stress in integrated circuits 失效
公开(公告)号：US06602798B1
公开(公告)日：2003-08-05
申请号：US09518154
申请日：2000-03-02
申请人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
发明人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
IPC分类号： H01L2131
CPC分类号： H01L21/32 , H01L21/0332
摘要： Stress resulting from silicon nitride is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride by varying the amount of hydride, such as dichlorosilane (DCS), mixed with ammonia. The silicon nitride can be graded in a substantially linear or non-linear fashion. Silicon nitride formed with higher levels of DCS mixed with ammonia is referred to as silicon rich nitride because of its relatively higher silicon content. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress from the silicon nitride is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, the stress from the silicon nitride is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.

4. 发明授权

US06703690B2 Apparatus for reducing isolation stress in integrated circuits 失效
标题翻译：降低集成电路隔离应力的方法和装置
公开(公告)号：US06703690B2
公开(公告)日：2004-03-09
申请号：US10188472
申请日：2002-07-02
申请人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
发明人： Randhir P. S. Thakur , Kevin G. Donohoe , Zhiqiang Wu , Alan R. Reinberg
IPC分类号： H01L2358
CPC分类号： H01L21/32 , H01L21/0332
摘要： Mechanical stress is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride. The silicon nitride can be graded in a substantially linear or non-linear fashion. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, stress is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.
摘要翻译：通过用具有梯度硅浓度的氮化硅形成氧化掩模来减小机械应力。通过改变氮化硅中的硅含量来实现分级。氮化硅可以以基本线性或非线性方式分级。在一个实施例中，渐变氮化硅可以用一种类型的非线性硅分级，突变结形成。在其它实施例中，氮化硅形成为在氮化硅生长期间或之后形成的各种形状。在一个实施例中，通过在两个氮化硅层之间形成多晶硅缓冲层来减小应力。在另一个实施例中，通过在衬底层上形成氮化硅来降低应力，衬底层又形成在基底层上。

5. 发明授权

US6157566A Reduced leakage DRAM storage unit 有权
公开(公告)号：US6157566A
公开(公告)日：2000-12-05
申请号：US550189
申请日：2000-04-14
申请人： Zhiqiang Wu , Randhir P S Thakur , Alan Reinberg , Kirk Prall
发明人： Zhiqiang Wu , Randhir P S Thakur , Alan Reinberg , Kirk Prall
IPC分类号： G11C11/404 , H01L27/108 , G11C11/40
CPC分类号： G11C11/404 , H01L27/108 , H01L27/10808
摘要： The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.

6. 发明授权

US06309975B1 Methods of making implanted structures 失效
标题翻译：植入结构的方法
公开(公告)号：US06309975B1
公开(公告)日：2001-10-30
申请号：US08818660
申请日：1997-03-14
申请人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
发明人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
IPC分类号： H01L2100
CPC分类号： H01L27/10852 , H01L21/2815 , H01L21/28525 , H01L21/30608 , H01L21/32134 , H01L21/76232 , H01L21/76237 , H01L21/7624 , H01L21/76838 , H01L21/76897 , H01L27/10817 , H01L28/60 , H01L29/66492 , H01L29/66575
摘要： Methods are disclosed for forming shaped structures of silicon-containing material with ion implantation and an etching process which is selective to silicon-containing material implanted to a certain concentration of ions or with an etching process which is selective to relatively unimplanted silicon-containing material. In general, the methods initially involve providing a layer of silicon-containing material such as polysilicon or epitaxial silicon on a semiconductor substrate. The layer of silicon-containing material is then masked, and ions are implanted into exposed portions of the layer of silicon-containing material. The mask is removed, and the aforementioned selective etching process is conducted to result in one of an implanted and a relatively unimplanted portion of the layer of silicon-containing material being etched away and the other left standing to form a shaped structure of silicon-containing material. One preferred selective etching process uses an etchant solution comprising a selected weight percentage of tetramethyl ammonium hydroxide in deionized water. The etchant solution etches relatively unimplanted silicon-containing material implanted up to 60 times faster than it etches silicon-containing material implanted to beyond a threshold concentration of ions. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.
摘要翻译：公开了用于通过离子注入形成含硅材料的成形结构的方法，以及对注入一定浓度的离子的含硅材料或对相对未被植入的含硅材料选择性的蚀刻工艺是选择性的蚀刻工艺。通常，该方法最初涉及在半导体衬底上提供诸如多晶硅或外延硅的含硅材料层。然后掩蔽含硅材料层，并将离子注入含硅材料层的暴露部分。去除掩模，并且进行上述选择性蚀刻工艺以导致被蚀刻掉的含硅材料层的注入和相对未被注入的部分中的一个，而另一个放置形成含硅的成形结构材料。一种优选的选择性蚀刻方法使用包含选定重量百分比的四甲基氢氧化铵在去离子水中的蚀刻剂溶液。蚀刻剂溶液蚀刻相对未被植入的含硅材料，其比注入超过阈值浓度离子的含硅材料蚀刻高达60倍。各种方法用于形成凸起形状的结构，成形开口，多晶硅插塞，电容器存储节点，环绕栅极晶体管，独立壁，互连线，沟槽电容器和沟槽隔离区域。

7. 发明授权

US06596648B2 Material removal method for forming a structure 有权
公开(公告)号：US06596648B2
公开(公告)日：2003-07-22
申请号：US10193850
申请日：2002-07-11
申请人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
发明人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
IPC分类号： H01L2100
CPC分类号： H01L27/10852 , H01L21/2815 , H01L21/28525 , H01L21/30608 , H01L21/32134 , H01L21/76232 , H01L21/76237 , H01L21/7624 , H01L21/76838 , H01L21/76897 , H01L27/10817 , H01L28/60 , H01L29/66492 , H01L29/66575
摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

8. 发明授权

US06599840B2 Material removal method for forming a structure 有权
公开(公告)号：US06599840B2
公开(公告)日：2003-07-29
申请号：US10194833
申请日：2002-07-11
申请人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
发明人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
IPC分类号： H01L2100
CPC分类号： H01L27/10852 , H01L21/2815 , H01L21/28525 , H01L21/30608 , H01L21/32134 , H01L21/76232 , H01L21/76237 , H01L21/7624 , H01L21/76838 , H01L21/76897 , H01L27/10817 , H01L28/60 , H01L29/66492 , H01L29/66575
摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

9. 发明授权

US06596642B2 Material removal method for forming a structure 失效
公开(公告)号：US06596642B2
公开(公告)日：2003-07-22
申请号：US10193801
申请日：2002-07-11
申请人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
发明人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
IPC分类号： H01L2100
CPC分类号： H01L27/10852 , H01L21/2815 , H01L21/28525 , H01L21/30608 , H01L21/32134 , H01L21/76232 , H01L21/76237 , H01L21/7624 , H01L21/76838 , H01L21/76897 , H01L27/10817 , H01L28/60 , H01L29/66492 , H01L29/66575
摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

10. 发明授权

US06461967B2 Material removal method for forming a structure 有权
标题翻译：用于形成结构的材料去除方法
公开(公告)号：US06461967B2
公开(公告)日：2002-10-08
申请号：US09907296
申请日：2001-07-16
申请人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
发明人： Zhiqiang Wu , Li Li , Thomas A. Figura , Kunal R. Parekh , Pai-Hung Pan , Alan R. Reinberg , Kin F. Ma
IPC分类号： H01L2100
CPC分类号： H01L27/10852 , H01L21/2815 , H01L21/28525 , H01L21/30608 , H01L21/32134 , H01L21/76232 , H01L21/76237 , H01L21/7624 , H01L21/76838 , H01L21/76897 , H01L27/10817 , H01L28/60 , H01L29/66492 , H01L29/66575
摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.
摘要翻译：公开了用于从具有对材料的低应力部分选择性的材料去除工艺从含硅和/或含锗材料形成成形结构的方法。通常，该方法最初在半导体衬底上提供一层材料。然后，其中具有均匀应力的材料被掩蔽，并且材料的一部分中的应力例如通过将离子注入未掩模部分中而减少。去除掩模，并且优选通过蚀刻工艺选择性地去除材料的高应力掩蔽部分。材料的低应力部分保留并形成成形结构。一种优选的选择性蚀刻方法使用基本蚀刻剂。各种方法用于形成凸起形状的结构，成形开口，多晶硅插塞，电容器存储节点，环绕栅极晶体管，独立壁，互连线，沟槽电容器和沟槽隔离区域。

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