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1. 发明申请

US20130154109A1 METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTERPOSER CAPABLE OF BEING REVERSE BIASED TO ACHIEVE REDUCED CAPACITANCE 审中-公开
标题翻译：降低导电性能的方法和可逆向实现降低电容的插入器的方法
公开(公告)号：US20130154109A1
公开(公告)日：2013-06-20
申请号：US13328332
申请日：2011-12-16
申请人： Ramnath Venkatraman , John W. Osenbach , Anwar Ali , Donald E. Hawk , Robert J. Madge
发明人： Ramnath Venkatraman , John W. Osenbach , Anwar Ali , Donald E. Hawk , Robert J. Madge
IPC分类号： H01L23/48 , H01L21/22 , H01L21/02
CPC分类号： H01L23/4926 , H01L23/49827 , H01L23/5384 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.
摘要翻译：本公开提供了具有导电路径的插入器，三维集成电路（3D IC），减小与插入器中的导电路径相关联的电容的方法和制造插值器的方法。在一个实施例中，插入器包括：（1）掺杂有掺杂剂的半导体衬底，（2）位于所述半导体衬底内的导电路径，并且被配置为提供穿过其中的电路径，以及（3）位于所述半导体衬底内的欧姆接触区域并被配置为接收背偏置电压。

2. 发明授权

US08624352B2 Mitigation of detrimental breakdown of a high dielectric constant metal-insulator-metal capacitor in a capacitor bank 有权
标题翻译：减轻电容器组中高介电常数金属 - 绝缘体 - 金属电容器的有害击穿
公开(公告)号：US08624352B2
公开(公告)日：2014-01-07
申请号：US12953624
申请日：2010-11-24
申请人： Bonnie E. Weir , Edward B. Harris , Ramnath Venkatraman
发明人： Bonnie E. Weir , Edward B. Harris , Ramnath Venkatraman
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.
摘要翻译： IC电容器组包括连接到一对导电迹线的多个高k金属 - 绝缘体金属（MIM）电容器。位于一对导电迹线之一的端部上的可熔痕迹形成连接在电源线之间的电容器柱，使得MIM电容器中的电介质的故障导致可熔痕迹至少部分地断开，由此限制了在电容柱。此外，制造IC电容器组的方法包括提供连接到一对导电迹线的多个高k金属 - 绝缘体金属（MIM）电容器，并且在一对导电迹线的端部上定位可熔迹线以形成连接在电源线之间的电容器柱，使得MIM电容器中的电介质的故障导致可熔痕迹至少部分地打开，从而限制电容器柱中的故障电流。

3. 发明授权

US07869251B2 SRAM based one-time-programmable memory 有权
标题翻译：基于SRAM的一次可编程存储器
公开(公告)号：US07869251B2
公开(公告)日：2011-01-11
申请号：US12239469
申请日：2008-09-26
申请人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors. Upon repeated cycling of the source-to-drain voltage, the targeted MOS transistor within the programming circuit breaks down and shorts across the gate, drain, and/or source of the transistor. When the system is returned to normal operation, the programming circuits will be connected to ground, Vdd or Vss and one of the two nodes of the SRAM cell circuit will be shorted through the programming circuit to ground, Vdd or Vss, thus, forcing a retention of the programmed data state.
摘要翻译：公开了一种用于提供基于SRAM存储器技术的快速响应一次可编程（OTP）存储器和MOS晶体管的固有击穿特性的方法和装置。 SRAM存储单元电路的每个存储单元连接到编程电路。编程电路由连接到SRAM存储器电路的两个交叉耦合反相器的存储节点（SN和SNB，其中SNB是SN的互补值）的两组MOS晶体管组成。将期望的数据组加载到电路中，然后通过施加并重复地循环编程电路的MOS晶体管的源极和漏极上的“老化”电压并接近特性的ON状态触发电压而被烧录双极结晶体管包含在MOS晶体管内。在重复循环源极至漏极电压之后，编程电路内的目标MOS晶体管在晶体管的栅极，漏极和/或源极之间分解和短路。当系统恢复正常运行时，编程电路将连接到地，Vdd或Vss，SRAM单元电路的两个节点之一将通过编程电路短路到地Vdd或Vss，从而强制保留编程数据状态。

4. 发明授权

US07440356B2 Modular design of multiport memory bitcells 有权
标题翻译：多端口存储器单元的模块化设计
公开(公告)号：US07440356B2
公开(公告)日：2008-10-21
申请号：US11487061
申请日：2006-07-13
申请人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： G11C8/00
CPC分类号： H01L27/11 , G11C8/16 , G11C11/412 , H01L27/1104
摘要： The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.
摘要翻译：本发明提供一种用于设计和模块化扩展多端口比特单元的系统和方法。描述了一种模块化设计方法，它降低了设计多端口位单元的复杂性，同时遵循了各种半导体制造提供商的DFM规则。模块化设计可以被解析成诸如读端口模块，写端口模块和可以容易地互连以构建多端口位单元的上拉模块的模块。这些模块还可以独立地定尺寸和组装以实现期望的读取边缘，写入边距，静态噪声容限以及读取访问时间和写入时间。

5. 发明申请

US20080013383A1 Modular design of multiport memory bitcells 有权
公开(公告)号：US20080013383A1
公开(公告)日：2008-01-17
申请号：US11487061
申请日：2006-07-13
申请人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： G11C7/10
CPC分类号： H01L27/11 , G11C8/16 , G11C11/412 , H01L27/1104
摘要： The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.

6. 发明授权

US07006370B1 Memory cell architecture 失效
标题翻译：存储单元架构
公开(公告)号：US07006370B1
公开(公告)日：2006-02-28
申请号：US10716259
申请日：2003-11-18
申请人： Subramanian Ramesh , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Subramanian Ramesh , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： G11C5/06
CPC分类号： G11C11/412 , H01L27/1104
摘要： A memory cell architecture is provided herein for increasing memory speed, performance and robustness within a highly compact memory cell layout. Though only a few embodiments are provided herein, a feature common to all embodiments includes a novel means for sharing one or more contact structures between vertically adjacent memory cells. In particular, one or more contact structures may be shared unequally between two vertically adjacent memory cells for reducing a vertical dimension, or length, of the memory cell. Other features are disclosed for producing the highly compact memory cell layout. The various features of the present invention may be combined to produce high-performance, high-density memory arrays.
摘要翻译：本文提供了一种存储单元架构，用于在高度紧凑的存储器单元布局内提高存储器速度，性能和鲁棒性。虽然本文仅提供了几个实施例，但是所有实施例共同的特征包括用于在垂直相邻的存储器单元之间共享一个或多个接触结构的新型装置。特别地，一个或多个接触结构可以在两个垂直相邻的存储器单元之间被不平等地共享，以减小存储单元的垂直尺寸或长度。公开了用于产生高度紧凑的存储单元布局的其它特征。本发明的各种特征可以组合以产生高性能，高密度的存储阵列。

7. 发明授权

US06713381B2 Method of forming semiconductor device including interconnect barrier layers 失效
标题翻译：形成包括互连阻挡层的半导体器件的方法
公开(公告)号：US06713381B2
公开(公告)日：2004-03-30
申请号：US10051262
申请日：2002-01-18
申请人： Alexander L. Barr , Suresh Venkatesan , David B. Clegg , Rebecca G. Cole , Olubunmi Adetutu , Stuart E. Greer , Brian G. Anthony , Ramnath Venkatraman , Gregor Braeckelmann , Douglas M. Reber , Stephen R. Crown
发明人： Alexander L. Barr , Suresh Venkatesan , David B. Clegg , Rebecca G. Cole , Olubunmi Adetutu , Stuart E. Greer , Brian G. Anthony , Ramnath Venkatraman , Gregor Braeckelmann , Douglas M. Reber , Stephen R. Crown
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/76801 , H01L21/76807 , H01L21/76813 , H01L21/76843 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L2223/54473 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05025 , H01L2224/05027 , H01L2224/0508 , H01L2224/05147 , H01L2224/05157 , H01L2224/05166 , H01L2224/05172 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05572 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01016 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01046 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/12042 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05155 , H01L2224/05164 , H01L2224/05169 , H01L2924/013 , H01L2924/0496 , H01L2924/0539 , H01L2924/0538 , H01L2924/0537
摘要： An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).
摘要翻译：互连覆盖半导体器件衬底（10）。在一个实施例中，导电阻挡层覆盖在互连的一部分上，钝化层（92）覆盖在导电阻挡层上，钝化层（92）具有暴露导电阻挡层（82）的部分的开口。在替代实施例中，钝化层（22）覆盖互连，钝化层（22）具有暴露互连的开口（24），并且导电阻挡层（32）覆盖开口（24）内的互连。

8. 发明授权

US5814557A Method of forming an interconnect structure 失效
标题翻译：形成互连结构的方法
公开(公告)号：US5814557A
公开(公告)日：1998-09-29
申请号：US650560
申请日：1996-05-20
申请人： Ramnath Venkatraman , Elizabeth J. Weitzman , Robert W. Fiordalice
发明人： Ramnath Venkatraman , Elizabeth J. Weitzman , Robert W. Fiordalice
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L23/53238 , H01L21/768 , H01L23/5226 , H01L23/53233 , H01L2924/0002
摘要： An interconnect structure (10) is formed by filling a dual damascene structure (12) with conductive material. A barrier layer (13) is formed to serve as a seed layer and to prevent the out diffusion of copper. A first conductive layer (14) is formed to fill a first portion (21) of the damascene structure (12). A second conductive layer (16) is then formed to complete the filling of a second portion (22) of the damascene structure. A polishing process is then used to remove any excess material.
摘要翻译：通过用导电材料填充双镶嵌结构（12）形成互连结构（10）。形成阻挡层（13）以用作种子层并防止铜的扩散。形成第一导电层（14）以填充镶嵌结构（12）的第一部分（21）。然后形成第二导电层（16）以完成镶嵌结构的第二部分（22）的填充。然后使用抛光工艺去除任何多余的材料。

9. 发明授权

US08738940B2 Power controller for SoC power gating applications 有权
标题翻译：用于SoC电源门控应用的电源控制器
公开(公告)号：US08738940B2
公开(公告)日：2014-05-27
申请号：US13226038
申请日：2011-09-06
申请人： Ramnath Venkatraman , Shashidhara S. Bapat , Ruggero Castagnetti
发明人： Ramnath Venkatraman , Shashidhara S. Bapat , Ruggero Castagnetti
IPC分类号： G06F1/00 , H03K19/00 , H03K17/00
CPC分类号： H03K19/0016
摘要： A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.
摘要翻译：冲击电流控制器包括连接的时钟模块，以基于对与输入的睡眠控制信号相对应的预设数量的时钟周期计数来提供延迟的睡眠控制信号。此外，引入电流控制器包括环形振荡器模块，其连接以基于对应于虚拟电源线电压的预设数量的环形振荡器周期来计数延迟的睡眠控制信号。一种控制加速电流的方法包括：基于对与输入的睡眠控制信号相对应的预设数量的时钟周期进行计数，提供延迟睡眠控制信号，并且基于对预定数量的环形振荡器周期进行计数来保持延迟的睡眠控制信号到虚拟电源线电压。

10. 发明授权

US08589853B2 Total power optimization for a logic integrated circuit 失效
标题翻译：逻辑集成电路的总功率优化
公开(公告)号：US08589853B2
公开(公告)日：2013-11-19
申请号：US13103461
申请日：2011-05-09
申请人： Benjamin Mbouombouo , Ramnath Venkatraman , Ruggero Castagnetti
发明人： Benjamin Mbouombouo , Ramnath Venkatraman , Ruggero Castagnetti
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/50 , G06F17/505 , G06F2217/78
摘要： A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.
摘要翻译：减少逻辑单元的总功耗的方法包括：选择对应于至少一个路径的逻辑单元的分布，在逻辑单元的分布中计算每个逻辑单元的动态到静态功率比，并将动态到静态功率比排列每个逻辑单元分成下组，中间组和上组逻辑单元。此外，该方法包括交换逻辑单元的下组和用于重构的中间组逻辑单元的逻辑单元的上组，并验证重构的中间组逻辑单元的路径定时。还提供了使用布尔方程和逻辑单元组来降低总功耗的方法。

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