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1. 发明授权

US06181212B2 Phase locked loop for generating two disparate, variable frequency signals 有权
标题翻译：锁相环产生两个不同的可变频率信号
公开(公告)号：US06181212B2
公开(公告)日：2001-01-30
申请号：US09238990
申请日：1999-01-28
申请人： Ramin Khoini-Poorfard , Hussein K. Mecklai
发明人： Ramin Khoini-Poorfard , Hussein K. Mecklai
IPC分类号： H03L7197
CPC分类号： H03C3/0933 , H03C3/40 , H03D7/163 , H03D7/165 , H03L7/1976 , H04B1/00 , H04B1/28 , H04B1/406
摘要： A method and apparatus for generating two disparate frequency reference signals using a single phase locked loop. The circuit includes a local oscillator for generating a reference signal and a phase comparator for comparing the reference signal with a feedback signal. The output of the phase comparator is converted to a first one of the desired output frequencies by a voltage controlled oscillator. That signal is also fed to a variable frequency divider circuit under control of a &Sgr;/&Dgr; converter which generates a lower frequency signal without creating a secondary frequency tone. The lower frequency signal is the second of the output frequencies. This signal also is fed back to the second input of the phase comparator through a fixed frequency divider.
摘要翻译：一种用于使用单个锁相环产生两个不同频率参考信号的方法和装置。电路包括用于产生参考信号的本地振荡器和用于将参考信号与反馈信号进行比较的相位比较器。相位比较器的输出通过压控振荡器转换成所需输出频率的第一个。该信号也在SIGMA / DELTA转换器的控制下馈送到可变分频器电路，该转换器产生较低频率信号而不产生辅助频率音调。低频信号是输出频率的第二个。该信号也通过固定分频器反馈到相位比较器的第二输入端。

2. 发明授权

US07279927B2 Integrated circuit with multiple power domains 有权
标题翻译：具有多个电源域的集成电路
公开(公告)号：US07279927B2
公开(公告)日：2007-10-09
申请号：US11052636
申请日：2005-02-07
申请人： John Thomas Falkowski , Bruce Godley Littlefield , Douglas D. Lopata , Hussein K. Mecklai , Stanley Reinhold
发明人： John Thomas Falkowski , Bruce Godley Littlefield , Douglas D. Lopata , Hussein K. Mecklai , Stanley Reinhold
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H02J1/14 , Y10T307/50
摘要： An integrated circuit having two or more power domains that include load circuits in different portions of the integrated circuit is disclosed. In order to conserve power, the circuits in one of the power domains are shut down by disconnecting the power source serving that domain. The load circuits in each power domain are buffered from the load circuits in other power domains by buffer cells. The buffer cells reduce leakage currents in the power domain that is shut down, by restricting data signals from the “live” power domain from reaching the shut-down power domain, and further by providing predetermined voltage signals to the load circuits in the shut-down power domain that are selected to minimize leakage currents in the inactive load circuits. The invention further provides a corresponding method for reducing power consumption in an integrated circuit having at least two power domains separated by a buffer cell.
摘要翻译：公开了一种具有两个或更多个功率域的集成电路，其中集成电路的不同部分包括负载电路。为了节省功率，通过断开服务于该域的电源来关闭其中一个电源域中的电路。每个功率域中的负载电路通过缓冲单元从其他电源域的负载电路缓冲。缓冲单元通过限制来自“实时”功率域的数据信号到达关闭功率域，从而减少关闭电源域中的漏电流，并进一步通过向闭环电源中的负载电路提供预定的电压信号，降压功率域被选择以使无效负载电路中的漏电流最小化。本发明还提供了一种用于降低集成电路中具有由缓冲单元隔开的至少两个功率域的功耗的相应方法。

3. 发明授权

US6167109A Compact buffer design for serial I/O 有权
标题翻译：串行I / O的紧凑型缓冲设计
公开(公告)号：US6167109A
公开(公告)日：2000-12-26
申请号：US315274
申请日：1999-05-20
申请人： Hussein K. Mecklai , Andrew Lawrence Webb
发明人： Hussein K. Mecklai , Andrew Lawrence Webb
IPC分类号： G06F5/01 , G11C19/00
CPC分类号： G11C19/00 , G06F5/015
摘要： A buffer design for use in digital signal processing for providing parallel shifting of digital data and serial output of the shifted data. The buffer includes an input shift register for receiving and shifting an input digital word, and one or more parallel shift registers connected to the input shift register for receiving and parallel shifting the shifted digital word output by the input shift register. An output shift register is connected to the parallel shift registers for shifting and serially outputting the shifted data word. The use of parallel shift registers in the inventive buffer allows for a more efficient use of chip surface area in the buffer design, thereby increasing overall chip yield and reducing chip cost.
摘要翻译：用于数字信号处理的缓冲器设计，用于提供数字数据的并行移位和移位数据的串行输出。缓冲器包括用于接收和移位输入数字字的输入移位寄存器和连接到输入移位寄存器的一个或多个并行移位寄存器，用于接收和并行移位由输入移位寄存器输出的移位数字字。输出移位寄存器连接到并行移位寄存器，用于移位和串行输出移位的数据字。在本发明的缓冲器中使用并行移位寄存器允许在缓冲器设计中更有效地使用芯片表面积，从而提高整体芯片产量并降低芯片成本。

4. 发明授权

US06412029B1 Method and apparatus for interfacing between a digital signal processor and a baseband circuit for wireless communication system 有权
标题翻译：用于在数字信号处理器和用于无线通信系统的基带电路之间进行接口的方法和装置
公开(公告)号：US06412029B1
公开(公告)日：2002-06-25
申请号：US09302071
申请日：1999-04-29
申请人： Hussein K. Mecklai , Andrew Lawrence Webb
发明人： Hussein K. Mecklai , Andrew Lawrence Webb
IPC分类号： G06F1314
CPC分类号： H04B1/0028 , H04B1/0003 , H04B1/0032 , H04B1/406
摘要： A method and apparatus for communicating transmit and receive data between a digital signal processor and the baseband processing circuitry in a digital communications station such as a digital cellular telephone. The invention utilizes a transmit buffer and a receive buffer for smoothing out the flow of data. TRANSMIT BUFFER EMPTY and RECEIVE BUFFER FULL interrupts indicating the need for data to be retrieved from the transmit buffer or sent to the receive buffer, respectively, are serviced by a DMA with translation circuitry rather than the DSP. The DMA with translation circuitry intercepts the interrupts and services them by transferring data directly to or from the DSP's RAM without disturbing the DSP. The translation circuitry also arbitrates between TRANSMIT BUFFER EMPTY and RECEIVE BUFFER FULL interrupts so as to service the RECEIVE BUFFER FULL interrupts first since they have stricter timing requirements.
摘要翻译：一种数字信号处理器与诸如数字蜂窝电话之类的数字通信站中的基带处理电路之间传送和接收数据的方法和装置。本发明利用发送缓冲器和接收缓冲器来平滑数据流。发送缓冲区空闲和接收缓冲区分别表示需要从发送缓冲区检索数据或发送到接收缓冲区的完全中断由具有转换电路而不是DSP的DMA服务。具有转换电路的DMA通过将数据直接传送到DSP的RAM而不影响DSP来截取中断并对其进行服务。翻译电路还在发送缓冲区空闲和接收缓冲区完全中断之间进行仲裁，以便首先为接收缓冲区完全中断服务，因为它们具有更严格的时序要求。

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