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1. 发明授权

US5887183A Method and system in a data processing system for loading and storing vectors in a plurality of modes 失效
标题翻译：用于以多种模式加载和存储向量的数据处理系统中的方法和系统
公开(公告)号：US5887183A
公开(公告)日：1999-03-23
申请号：US368173
申请日：1995-01-04
申请人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Terry L. Lyon , Brett Olsson , James B. Shearer
发明人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Terry L. Lyon , Brett Olsson , James B. Shearer
IPC分类号： G06F9/312 , G06F15/80
CPC分类号： G06F9/30043 , G06F15/8092 , G06F9/30036
摘要： A vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern. Thereafter, the elements are transferred, in a first order, from the input storage area into a vector register interface unit. From the vector register interface unit, the elements are transferred to an output storage area and stored in addressable locations in one of a plurality of preselected patterns. The input storage area may be implemented with cache memory or a register array. The output storage area may be implemented with a cache memory or a register array. The first pattern in the input storage area may include alternating real and imaginary elements. The plurality of preselected patterns may include a reversed order pattern, or a separation of real and imaginary elements into two vector registers.
摘要翻译：具有多个元素的向量存储在输入存储区域中，其中矢量元素以第一模式存储。此后，元件以第一顺序从输入存储区域传送到向量寄存器接口单元。从矢量寄存器接口单元，将元件传送到输出存储区域，并以多个预选图案之一存储在可寻址位置。输入存储区域可以由高速缓冲存储器或寄存器阵列来实现。输出存储区域可以用高速缓冲存储器或寄存器阵列来实现。输入存储区域中的第一图案可以包括交替的实数和虚部元素。多个预选图案可以包括相反的顺序图案，或者将实数元素和虚构元素分离成两个向量寄存器。

2. 发明授权

US5680338A Method and system for vector processing utilizing selected vector elements 失效
标题翻译：利用选定向量元素进行向量处理的方法和系统
公开(公告)号：US5680338A
公开(公告)日：1997-10-21
申请号：US368172
申请日：1995-01-04
申请人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Brett Olsson , James B. Shearer
发明人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred G. Gustavson , Mark A. Johnson , Brett Olsson , James B. Shearer
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： In a vector processing system for processing vector calculations utilizing a portion of a vector comprising a plurality of elements, means for receiving a vector and a vector processing command are provided. The vector processing system also includes means for receiving and storing a start-element value and an end-element value. An arithmetic logic unit is coupled to the means for receiving the vector, the means for receiving the vector processing command, and the means for receiving the start-element and end-element values. The arithmetic logic unit also includes means for executing the vector processing command utilizing only one or more of the elements in the vector, which are selected by the start-element value and the end-element value.
摘要翻译：在使用包括多个元素的向量的一部分来处理向量计算的向量处理系统中，提供了用于接收向量和向量处理命令的装置。矢量处理系统还包括用于接收和存储起始元素值和终止元素值的装置。算术逻辑单元耦合到用于接收向量的装置，用于接收向量处理命令的装置和用于接收起始元素和终止元素值的装置。算术逻辑单元还包括仅利用向量中的一个或多个元素来执行向量处理命令的装置，其由起始元素值和终止元素值选择。

3. 发明授权

US5825677A Numerically intensive computer accelerator 失效
标题翻译：数字密集型计算机加速器
公开(公告)号：US5825677A
公开(公告)日：1998-10-20
申请号：US619456
申请日：1996-03-20
申请人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred Gehrung Gustavson , Mark Alan Johnson , Brett Olsson
发明人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred Gehrung Gustavson , Mark Alan Johnson , Brett Olsson
IPC分类号： G06F17/16 , G06F15/80
CPC分类号： G06F15/8092 , G06F15/8023
摘要： A matrix processing unit is described which permits high speed numerical computation. The processing unit is a vector processing unit which is formed from a plurality of processing elements. The Ith processing unit has a set of N registers within which the Ith elements or words of N vectors of data are stored. Each processing element has an arithmetic unit which is capable of performing arithmetic operations on the N elements in the set of N registers. Each vector of data has K elements. Therefore, there are K processing elements. A vector operation of the matrix processing unit simultaneously performs the same operation on all elements of two vectors or more. A subsequent vector operation can be performed within one machine cycle time after the preceding vector operation.
摘要翻译：描述了允许高速数值计算的矩阵处理单元。处理单元是由多个处理元件形成的矢量处理单元。第I处理单元具有一组N个寄存器，其中存储了N个数据向量的第I个元素或单词。每个处理元件具有能够对N个寄存器组中的N个元素执行算术运算的算术单元。每个数据矢量都有K个元素。因此，有K个处理元素。矩阵处理单元的向量运算同时对两个向量的全部要素进行相同的运算。可以在先前的矢量操作之后的一个机器周期内执行随后的矢量操作。

4. 发明授权

US5758176A Method and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing system 失效
标题翻译：提供用于在超标量数据处理系统内执行单指令多数据操作的单指令多数据执行单元的方法和系统
公开(公告)号：US5758176A
公开(公告)日：1998-05-26
申请号：US313970
申请日：1994-09-28
申请人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred Gehrung Gustavson , Mark Alan Johnson , Brett Olsson
发明人： Ramesh Chandra Agarwal , Randall Dean Groves , Fred Gehrung Gustavson , Mark Alan Johnson , Brett Olsson
IPC分类号： G06F9/302 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3001 , G06F15/8007 , G06F15/8092 , G06F9/3885 , G06F9/3887
摘要： A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations. Once the control unit within the SIMD execution unit receives a vector instruction, the control unit translates the instruction into commands for execution by selected processing elements within the SIMD execution unit. If such a vector instruction requires access to memory, a fixed point execution unit within the superscalar processor may be utilized to calculate a memory address which is then utilized by the SIMD execution unit to access memory.
摘要翻译：提供了与超标量数据处理系统结合使用的单指令多数据（SIMD）执行单元。 SIMD执行单元耦合到超标量处理器内的分支执行单元。分支执行单元从存储器取出指令，并通过指令总线向SIMD执行单元分派向量处理指令。 SIMD执行单元包括用于执行算术运算的控制单元和多个处理元件。处理元件还包括具有多个寄存器的寄存器文件和耦合到寄存器文件的算术逻辑单元。算术逻辑单元可以包括用于执行定点矢量计算的定点单元和用于执行浮点矢量计算的浮点单元。一旦SIMD执行单元中的控制单元接收到向量指令，则控制单元将该指令转换为SIMD执行单元内的选定处理元件执行的命令。如果这样的向量指令需要访问存储器，则可以利用超标量处理器内的固定点执行单元来计算存储器地址，然后SIMD执行单元利用存储器地址访问存储器。

5. 发明授权

US5721854A Method and apparatus for dynamic conversion of computer instructions 失效
标题翻译：计算机指令的动态转换方法和装置
公开(公告)号：US5721854A
公开(公告)日：1998-02-24
申请号：US703804
申请日：1996-08-27
申请人： Mahmut Kemal Ebcioglu , Randall Dean Groves
发明人： Mahmut Kemal Ebcioglu , Randall Dean Groves
IPC分类号： G06F9/318 , G06F9/38 , G06F9/45
CPC分类号： G06F9/3017 , G06F9/3853 , G06F9/3885
摘要： An instruction cache design which converts a sequential instruction stream into a compound format in the instruction cache. The conversion from sequential instructions to compound instructions is performed by an instruction stream interpreter unit (ISU), which is placed between the instruction cache and main memory. The conversion process is performed when an instruction cache miss occurs. Each line in the instruction cache contains a single compound instruction. The format of this compound instruction is transparent to programmers and will vary depending on the number of execution units which are to be supported.
摘要翻译：指令高速缓存设计，其将顺序指令流转换为指令高速缓存中的复合格式。从顺序指令到复合指令的转换由位于指令高速缓存和主存储器之间的指令流解释器单元（ISU）执行。当指令高速缓存未命中时执行转换处理。指令高速缓存中的每一行包含单个复合指令。该复合指令的格式对程序员是透明的，并且将根据要支持的执行单元的数量而有所不同。

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