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1. 发明授权

US06351150B1 Low switching activity dynamic driver for high performance interconnects 失效
标题翻译：低开关活动动态驱动程序，用于高性能互连
公开(公告)号：US06351150B1
公开(公告)日：2002-02-26
申请号：US09658793
申请日：2000-09-11
申请人： Ram K. Krishnamurthy , Mark A. Anders , Atila Alvandpour
发明人： Ram K. Krishnamurthy , Mark A. Anders , Atila Alvandpour
IPC分类号： H03K19096
CPC分类号： H03K19/0016 , H03K19/01855
摘要： A high performance interconnect that utilizes dynamic driver technology is capable of reduced power operation during periods of low data switching activity. Circuitry is provided that limits the performance of an evaluation operation in the dynamic driver circuitry to clock cycles during which a present input bit of the interconnect differs from a previous input bit. Thus, the evaluation operation and subsequent precharge of the driver output is performed sparingly during periods of low data switching activity. An output circuit is also provided for decoding the data stream flowing through the interconnect at the receiver end thereof. Using the principles of the present invention, it is possible to achieve the performance advantages of dynamic drivers with the switching activity of interconnects that use static CMOS technology.
摘要翻译：利用动态驱动技术的高性能互连能够在低数据交换活动期间降低功耗。提供了电路，其将动态驱动器电路中的评估操作的性能限制为时钟周期，在该周期期间，互连的当前输入位与先前的输入位不同。因此，在低数据切换活动的时段期间，谨慎地执行驱动器输出的评估操作和随后的预充电。还提供了一个输出电路，用于解码在其接收端处流经互连的数据流。使用本发明的原理，可以通过使用静态CMOS技术的互连的交换活动来实现动态驱动器的性能优点。

2. 发明授权

US06614680B2 Current leakage reduction for loaded bit-lines in on-chip memory structures 有权
公开(公告)号：US06614680B2
公开(公告)日：2003-09-02
申请号：US10172277
申请日：2002-06-13
申请人： Atila Alvandpour , Ram K. Krishnamurthy , Siva G. Narendra
发明人： Atila Alvandpour , Ram K. Krishnamurthy , Siva G. Narendra
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

3. 发明授权

US06353342B1 Integrated circuit bus architecture including a full-swing, clocked, common-gate receiver for fast on-chip signal transmission 有权
标题翻译：集成电路总线架构，包括全频，时钟，共门接收器，用于快速片上信号传输
公开(公告)号：US06353342B1
公开(公告)日：2002-03-05
申请号：US09702121
申请日：2000-10-30
申请人： Atila Alvandpour , Soumyanath Krishnamurthy , Ram K. Krishnamurthy
发明人： Atila Alvandpour , Soumyanath Krishnamurthy , Ram K. Krishnamurthy
IPC分类号： G11C706
CPC分类号： H04L25/0292 , H04L25/0278 , H04L25/028
摘要： An integrated circuit (IC) bus architecture is disclosed. The bus architecture includes a receiver for fast on-chip signal transmission. The receiver includes a first gate device having one terminal connected to a voltage source and a gate terminal connectable to receive a sense signal. A second gate device includes one terminal connected to another terminal of the first gate device, a gate terminal connectable to receive the sense signal and another terminal serving as an input terminal of the receiver and connectable to an interconnect bus to receive input signals from other components on the IC chip. The receiver also includes a third gate device having one terminal connected to a voltage source and another terminal serving as an output terminal of the receiver and connected to the other terminal of the first gate device. The receiver further includes an inverter having an input terminal connected to the output of the receiver and having an output terminal connected to a gate terminal of the third gate device. The input of the receiver is capable of being pre-discharged to a low signal and the output of the receiver is capable of being pre-charged to a high signal for substantially instantaneous transmission of input signals received by the receiver.
摘要翻译：公开了一种集成电路（IC）总线架构。总线架构包括用于快速片上信号传输的接收器。接收机包括具有连接到电压源的一个端子和可连接以接收感测信号的栅极端子的第一栅极器件。第二栅极器件包括连接到第一栅极器件的另一个端子的一个端子，可连接的感测信号的栅极端子和用作接收器的输入端子的另一个端子，并且可连接到互连总线以从其它部件接收输入信号在IC芯片上。接收机还包括具有连接到电压源的一个端子和用作接收器的输出端的另一个端子并连接到第一门装置的另一端的第三门装置。接收机还包括一个反相器，其具有连接到接收器的输出的输入端，并且具有连接到第三门装置的栅极端的输出端。接收机的输入能够被预放电到低信号，并且接收机的输出能够被预充电到高信号，以便接收器接收的输入信号的基本瞬时传输。

4. 发明授权

US06919737B2 Voltage-level converter 失效
标题翻译：电压电平转换器
公开(公告)号：US06919737B2
公开(公告)日：2005-07-19
申请号：US10010737
申请日：2001-12-07
申请人： Atila Alvandpour , Ram K. Krishnamurthy
发明人： Atila Alvandpour , Ram K. Krishnamurthy
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018521
摘要： A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage. In an alternative embodiment, a method for converting a first logic voltage level to a second logic voltage level includes transmitting a logic signal from a logic unit having an output voltage swing of between a first voltage level and a second voltage level, receiving the logic signal at a logic circuit having a pull-up transistor and an output voltage swing between a third voltage level and a fourth voltage level, and turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level and the first voltage level.
摘要翻译：描述电压电平转换器和将第一逻辑电压电平转换到第二逻辑电压电平的方法。在一个实施例中，电压电平转换器将连接到第一电源电压的第一逻辑单元连接到与第二电源电压连接的第二逻辑单元。电压电平转换器包括连接到第二电源电压的至少一个晶体管。所述至少一个晶体管具有其绝对值大于或等于所述第二电源电压和所述第一电源电压之间的差的绝对值的阈值电压。在替代实施例中，用于将第一逻辑电压电平转换为第二逻辑电压电平的方法包括从具有在第一电压电平和第二电压电平之间的输出电压摆幅的逻辑单元传输逻辑信号，接收逻辑信号在具有上拉晶体管的逻辑电路和在第三电压电平和第四电压电平之间的输出电压摆幅，并且当所述逻辑信号具有略大于所述第三电压电平和第一电压电平。

5. 发明授权

US06590801B2 Current leakage reduction for loaded bit-lines in on-chip memory structures 有权
公开(公告)号：US06590801B2
公开(公告)日：2003-07-08
申请号：US10172106
申请日：2002-06-13
申请人： Atila Alvandpour , Ram K. Krishnamurthy , Siva G. Narendra
发明人： Atila Alvandpour , Ram K. Krishnamurthy , Siva G. Narendra
IPC分类号： G11C1140
CPC分类号： G11C11/412
摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

6. 发明授权

US06549040B1 Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates 有权
标题翻译：具有双输出产生能力的漏电保护器，用于深亚微米宽多米诺骨门
公开(公告)号：US06549040B1
公开(公告)日：2003-04-15
申请号：US09608683
申请日：2000-06-29
申请人： Atila Alvandpour , Krishnamurthy Soumyanath , Ram K. Krishnamurthy
发明人： Atila Alvandpour , Krishnamurthy Soumyanath , Ram K. Krishnamurthy
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.
摘要翻译：一种电路，包括输入时钟信号以接收时钟信号，输入至少一个数据信号以接收至少一个数据信号，以及多输入条件反相器以接收时钟信号和数据信号，并产生动态输出。电路还包括条件保持器电路，用于在时钟评估和动态输出为高时为动态输出节点充电。

7. 发明授权

US6137319A Reference-free single ended clocked sense amplifier circuit 有权
标题翻译：无参考单端时钟读出放大器电路
公开(公告)号：US6137319A
公开(公告)日：2000-10-24
申请号：US302677
申请日：1999-04-30
申请人： Ram K. Krishnamurthy , Atila Alvandpour , Reed D. Spotten
发明人： Ram K. Krishnamurthy , Atila Alvandpour , Reed D. Spotten
IPC分类号： G11C7/06 , H03F3/45 , H03K5/24
CPC分类号： G11C7/067 , H03F3/45188 , H03K5/2481 , H03K5/249
摘要： In some embodiments, the invention includes a reference-free single ended sense amplifier. The sense amplifier includes first and second transistors in a differential pair, the first transistor having a control terminal connected to an input conductor to receive an intermediate signal, the first transistor having a data terminal connected to a node, and the second transistor having a control terminal coupled to the node. The sense amplifier further includes a cross-coupled inverter latch having a first inverter coupled to the first transistor through the node and a second inverter coupled to the second transistor. In some embodiments, the control terminal of the second transistor is tied to the node. The first and second transistors of the differential pair may be pFET transistors or nFET transistors or a combination of them. In some embodiments, the sense amplifier is includes as a part of a domino logic gate. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，本发明包括一个无参考的单端读出放大器。感测放大器包括差分对中的第一和第二晶体管，第一晶体管具有连接到输入导体的控制端以接收中间信号，第一晶体管具有连接到节点的数据端，并且第二晶体管具有控制终端耦合到节点。读出放大器还包括交叉耦合的反相器锁存器，其具有通过节点耦合到第一晶体管的第一反相器和耦合到第二晶体管的第二反相器。在一些实施例中，第二晶体管的控制端被连接到节点。差分对的第一和第二晶体管可以是pFET晶体管或nFET晶体管或它们的组合。在一些实施例中，读出放大器包括作为多米诺逻辑门的一部分。描述和要求保护其他实施例。

8. 发明授权

US06751141B1 Differential charge transfer sense amplifier 失效
标题翻译：差分电荷传输读出放大器
公开(公告)号：US06751141B1
公开(公告)日：2004-06-15
申请号：US10305703
申请日：2002-11-26
申请人： Atila Alvandpour , Manoj Sinha , Ram K. Krishnamurthy
发明人： Atila Alvandpour , Manoj Sinha , Ram K. Krishnamurthy
IPC分类号： G11C702
CPC分类号： G11C7/065 , G11C7/12
摘要： A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port. This charge transfer scheme allows a differential voltage to quickly develop at the ports, thereby providing a fast latch and read operation with reduced power consumption. Bitline voltage swing may also be reduced to reduce power consumption.
摘要翻译：一种用于读取SRAM中的存储单元的读出放大器，读出放大器包括两个栅极偏置的pMOSFET，每个对应于选定的位线。两个栅极偏置的pMOSFET的栅极将其栅极偏置到偏置电压，其源极通过列选择晶体管耦合到所选位线，并且其漏极通过传输晶体管耦合到两个交叉耦合的反相器的两个端口，交叉耦合的逆变器形成锁存器。在选择的位线对已被预充电并且预充电阶段结束之后，两个栅极偏置的pMOSFET中的一个快速进入其亚阈值区域，其中一个位线通过其相应的存储单元放电，从而切断位线的电容从感测放大器。当通过晶体管使能时，两个pMOSFET中的另一个允许显着的位线电荷通过其对应的传输晶体管传输到其相应的端口，而相对较小的电荷被传送到另一个端口。该电荷转移方案允许在端口处快速产生差分电压，从而以降低的功率消耗提供快速锁存和读取操作。位线电压摆幅也可以降低以降低功耗。

9. 发明授权

US06493254B1 Current leakage reduction for loaded bit-lines in on-chip memory structures 失效
标题翻译：片上存储器结构中加载位线的电流泄漏减少
公开(公告)号：US06493254B1
公开(公告)日：2002-12-10
申请号：US09896348
申请日：2001-06-28
申请人： Atila Alvandpour , Ram K. Krishnamurthy , Siva G. Narendra
发明人： Atila Alvandpour , Ram K. Krishnamurthy , Siva G. Narendra
IPC分类号： G11C1140
CPC分类号： G11C11/412
摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.
摘要翻译：本发明的实施例涉及具有重负载位线的存储器电路，并且其中读取访问或传输晶体管中的漏电流的影响减小或漏电流减小。

10. 发明授权

US06707708B1 Static random access memory with symmetric leakage-compensated bit line 失效
标题翻译：具有对称泄漏补偿位线的静态随机存取存储器
公开(公告)号：US06707708B1
公开(公告)日：2004-03-16
申请号：US10241791
申请日：2002-09-10
申请人： Atila Alvandpour , Dinesh Somasekhar , Steven K. Hsu , Ram K. Krishnamurthy , Vivek K. De
发明人： Atila Alvandpour , Dinesh Somasekhar , Steven K. Hsu , Ram K. Krishnamurthy , Vivek K. De
IPC分类号： G11C1100
CPC分类号： G11C11/412 , G11C11/419
摘要： An eight-cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to ground and coupled to the local bit lines and the cross-coupled inverters so that sub-threshold leakage currents to and from the local bit lines for a memory cell not being read are balanced.
摘要翻译：用于静态随机存取存储器的八单元，存储单元包括用于存储信息位的交叉耦合反相器，连接到局部位线的两个存取nMOSFET以访问所存储的信息位，以及两个nMOSFET，每个具有连接到地的栅极和耦合到本地位线和交叉耦合的反相器，使得到达和从本地位线到不被读取的存储器单元的子阈值泄漏电流被平衡。

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