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    • 1. 发明授权
    • Single layer polycrystalline silicon split-gate EEPROM cell having a
buried control gate
    • 具有埋置控制栅极的单层多晶硅分离栅极EEPROM单元
    • US5844271A
    • 1998-12-01
    • US517495
    • 1995-08-21
    • Rakesh SethiWenchi Ting
    • Rakesh SethiWenchi Ting
    • G11C16/04H01L27/115H01L29/423H01L29/788
    • H01L29/7885G11C16/0425H01L27/115H01L29/42324
    • An electrically-erasable programmable read-only memory (EEPROM) cell includes a split-gate read transistor and a buried N-plate control gate. The split gate transistor includes a drain and source regions formed in a P-type silicon substrate with a channel formed therebetween. Silicon dioxide is disposed over the drain, channel and source regions wherein the oxide overlying the drain and a portion of the channel is thicker compared to the thickness of the oxide overlying the remainder of the channel and the source. A layer of polycrystalline silicon is disposed over the channel. The buried N-plate control gate is spaced laterally from the source, drain, and channel regions. The floating gate overlying the channel extends also over the buried N-plate control gate. The split gate structure effectively realizes a pair of in-series gates, each having a different threshold voltage in accordance with the thickness of the oxide used. The voltages applied to the N-plate region are capacitively coupled to the floating gate. The potential on the floating gate in turn causes activation of the transistors formed by the split-gate structure, depending on the existing charge on the floating gate.
    • 电可擦除可编程只读存储器(EEPROM)单元包括分离栅极读取晶体管和掩埋N板控制栅极。 分离栅晶体管包括形成在P型硅衬底中的漏极和源极区域,其间形成有沟道。 二氧化硅设置在漏极,沟道和源极区域之上,其中覆盖漏极的氧化物和沟道的一部分与覆盖沟道和源的其余部分的氧化物的厚度相比更厚。 多晶硅层设置在通道上。 掩埋的N极板控制栅极与源极,漏极和沟道区域横向间隔开。 覆盖通道的浮动栅极还在掩埋的N极板控制栅极上延伸。 分离栅极结构有效地实现了一对串联栅极,每对栅极具有根据所用氧化物的厚度的不同阈值电压。 施加到N板区域的电压电容耦合到浮动栅极。 浮动栅极上的电位依次由浮栅的现有电荷导致由分闸门结构形成的晶体管的激活。