专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5448567A Control architecture for ATM networks 失效
标题翻译： ATM网络的控制架构
公开(公告)号：US5448567A
公开(公告)日：1995-09-05
申请号：US97683
申请日：1993-07-27
申请人： Rajiv Dighe , Alexander T. Ishii , Gopalakrishnan Ramamurthy
发明人： Rajiv Dighe , Alexander T. Ishii , Gopalakrishnan Ramamurthy
IPC分类号： H04Q3/00 , H04L12/56 , H04Q11/04 , H04J3/24
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5637 , H04L2012/564 , H04L2012/5645
摘要： A control method and architecture is described for an ATM network carrying connectionless data traffic. The method is capable of integrating connection-oriented as well as connectionless traffic. The method takes advantage of the quasi-deterministic nature of the traffic emanating from a source that is being shaped by the leaky bucket shaping algorithm. Alternative methods are provided if such a shaping algorithm is not provided by the CPE which methods still guarantee performance that equals or exceeds shared media networks such as FDDI. Hardware and software embodiments of the methods are disclosed. The invention is particularly applicable to LANs and hubs.
摘要翻译：描述了一种用于承载无连接数据流量的ATM网络的控制方法和架构。该方法能够集成面向连接和无连接的流量。该方法利用由泄漏桶整形算法形成的源发出的流量的准确定性。如果CPE不提供这种整形算法，那么提供替代方法，哪些方法仍然保证等于或超过诸如FDDI的共享媒体网络的性能。公开了该方法的硬件和软件实施例。本发明特别适用于LAN和集线器。

2. 发明授权

US06556571B1 Fast round robin priority port scheduler for high capacity ATM switches 失效
标题翻译：快速循环优先端口调度程序用于高容量ATM交换机
公开(公告)号：US06556571B1
公开(公告)日：2003-04-29
申请号：US09317964
申请日：1999-05-25
申请人： Sharif M. Shahrier , Alexander T. Ishii
发明人： Sharif M. Shahrier , Alexander T. Ishii
IPC分类号： H04L1256
CPC分类号： H04L49/3081 , H04L49/203 , H04L49/255 , H04L2012/5635 , H04L2012/5651 , H04L2012/5679 , H04Q11/0478
摘要： A novel architecture and implementation of a Round-Robin Scheduler (RRS) for high capacity ATM switches is presented. A port is selected from a set of alternating real-time/non real-time priority ports, based on the priority of the port, the minimum cell-rate (MCR) assigned to the ports and the backpressure signals coming from the output buffers. A fast implementation of the scheduler was derived using a binary tree structure. The nodes in the binary tree act as “cut through” switches, and thus the scheduler is able to operate at high speed. This scheduler is amenable for implementation in high speed silicon technology. It is compact in terms of logic gate requirements, very scalable and is a viable option in Gigabit ATM switches.
摘要翻译：提出了一种用于大容量ATM交换机的轮回调度程序（RRS）的新颖架构和实现。基于端口的优先级，分配给端口的最小信元速率（MCR）和来自输出缓冲器的背压信号，从一组交替实时/非实时优先端口中选择一个端口。调度程序的快速实现是使用二叉树结构派生的。二叉树中的节点作为“切换”开关，因此调度程序能够高速运行。该调度程序适用于高速硅技术的实现。它在逻辑门要求方面非常紧凑，非常可扩展，并且在千兆位ATM交换机中是可行的选择。

3. 发明授权

US08461873B2 Resonant clock and interconnect architecture for digital devices with multiple clock networks 有权
标题翻译：具有多个时钟网络的数字设备的谐振时钟和互连架构
公开(公告)号：US08461873B2
公开(公告)日：2013-06-11
申请号：US13103985
申请日：2011-05-09
申请人： Alexander T. Ishii , Marios C. Papaefthymiou
发明人： Alexander T. Ishii , Marios C. Papaefthymiou
IPC分类号： H03K19/096
CPC分类号： G06F1/10
摘要： A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).
摘要翻译：提出了一种时钟和数据分配网络，无需缓冲器分配时钟和数据信号，从而实现非常低的抖动，偏移，松动的时序要求和能耗。这种网络使用谐振驱动器，并且通常可应用于诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）的架构，以及具有以各种时钟频率工作的多个时钟网络的其他半导体器件，以及高性能和低功率时钟要求，如微处理器，专用集成电路（ASIC）和片上系统（SOC）。

4. 发明申请

US20090027085A1 RESONANT CLOCK AND INTERCONNECT ARCHITECTURE FOR DIGITAL DEVICES WITH MULTIPLE CLOCK NETWORKS 有权
标题翻译：具有多个时钟网络的数字设备的谐振时钟和互连结构
公开(公告)号：US20090027085A1
公开(公告)日：2009-01-29
申请号：US12125009
申请日：2008-05-21
申请人： Alexander T. Ishii , Marios C. Papaefthymiou
发明人： Alexander T. Ishii , Marios C. Papaefthymiou
IPC分类号： H03K19/00 , G06F1/04 , H03K3/00
CPC分类号： G06F1/10
摘要： A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).
摘要翻译：提出了一种时钟和数据分配网络，无需缓冲器分配时钟和数据信号，从而实现非常低的抖动，偏移，松动的时序要求和能耗。这种网络使用谐振驱动器，并且通常可应用于诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）的架构，以及具有以各种时钟频率工作的多个时钟网络的其他半导体器件，以及高性能和低功率时钟要求，如微处理器，专用集成电路（ASIC）和片上系统（SOC）。

5. 发明授权

US06389019B1 Time-based scheduler architecture and method for ATM networks 失效
标题翻译：基于时间的调度器架构和ATM网络的方法
公开(公告)号：US06389019B1
公开(公告)日：2002-05-14
申请号：US09040311
申请日：1998-03-18
申请人： Ruixue Fan , Brian L. Mark , Gopalakrishan Ramamurthy , Alexander T. Ishii
发明人： Ruixue Fan , Brian L. Mark , Gopalakrishan Ramamurthy , Alexander T. Ishii
IPC分类号： H04L1256
CPC分类号： H04L12/5602 , H04L12/5601 , H04L47/12 , H04L47/22 , H04L2012/5651 , H04L2012/5679 , H04Q11/0478
摘要： A flexible and scalable architecture and method that implements dynamic rate control scheduling in an ATM switch. The scheduler shapes a large number of streams according to rate values computed dynamically based on switch congestion information. To handle a large range of bit rates, a plurality of timewheels are employed with different time granularities. The streams are assigned dynamically to the timewheels based on computed rate values. The shaper architecture and method support priority levels for arbitrating among streams which are simultaneously eligible to transmit.
摘要翻译：一种在ATM交换机中实现动态速率控制调度的灵活且可扩展的架构和方法。调度器根据基于交换机拥塞信息动态计算的速率值来形成大量流。为了处理大范围的比特率，采用具有不同时间粒度的多个时间轮。基于计算的速率值，将动态流分配给时间轮。整形器架构和方法支持同时有资格传输的流之间的仲裁优先级。

6. 发明申请

US20110210761A1 Resonant Clock And Interconnect Architecture For Digital Devices With Multiple Clock Networks 有权
标题翻译：具有多个时钟网络的数字设备的谐振时钟和互连架构
公开(公告)号：US20110210761A1
公开(公告)日：2011-09-01
申请号：US13103985
申请日：2011-05-09
申请人： Alexander T. Ishii , Marios C. Papaefthymiou
发明人： Alexander T. Ishii , Marios C. Papaefthymiou
IPC分类号： H03K19/096
CPC分类号： G06F1/10
摘要： A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs), as well as other semiconductor devices with multiple clock networks operating at various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, applications specific integrated circuits (ASICs), and Systems-on-a-Chip (SOCs).
摘要翻译：提出了一种时钟和数据分配网络，无需缓冲器分配时钟和数据信号，从而实现非常低的抖动，偏移，松动的时序要求和能耗。这种网络使用谐振驱动器，并且通常可应用于诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）的架构，以及具有以各种时钟频率工作的多个时钟网络的其他半导体器件，以及高性能和低功率时钟要求，如微处理器，专用集成电路（ASIC）和片上系统（SOC）。

7. 发明授权

US5644499A Retiming gated-clocks and precharged circuit structures 失效
标题翻译：重新定时门控时钟和预充电电路结构
公开(公告)号：US5644499A
公开(公告)日：1997-07-01
申请号：US525815
申请日：1995-09-07
申请人： Alexander T. Ishii
发明人： Alexander T. Ishii
IPC分类号： G06F17/50 , H03K5/13 , G06F17/10
CPC分类号： G06F17/5045 , H03K5/13
摘要： A general set of timing constraints, along with methods for computing the "critical" elements of the set, i.e., the elements of the set that, if satisfied, are sufficient to guarantee proper circuit timing, enables retiming of VLSI systems incorporating gated clock signals and/or precharged circuit structures without changing the input/output behavior of the system. In one method, either the clock signal used by a system component is changed or alternatively, a new clock signal is generated for use in the system. In another method, a system component is retimed by retiming other system components. In a further method, multiple critical paths for each pair of components comprising the system are computed. The most critical path for each pair of components is selected and if the most critical path for a pair of components is not properly timed, one component of the pair is retimed in order to properly time the pair of components. If the most critical path is properly timed, or is properly timed after retiming, the procedure is repeated for another pair of components until each pair of components is properly timed so that the VLSI system is, in turn, retimed.
摘要翻译：一组一组时序约束，以及用于计算集合的“关键”元素的方法，即集合的元素，如果满足，足以保证正确的电路时序，则可以重新定时并入门控时钟信号和/或预充电电路结构，而不改变系统的输入/输出特性。在一种方法中，由系统组件使用的时钟信号被改变，或者替代地，生成用于系统的新的时钟信号。在另一种方法中，系统组件通过重定时其他系统组件来重新定时。在另一种方法中，计算包括系统的每对组件的多个关键路径。选择每对组件的最关键路径，如果一对组件的最关键路径未正确定时，则重新对该对组件中的一个组件进行重新定时，以便对该组件进行适当的时间。如果最关键的路径被正确定时，或者在重新定时之后被正确定时，则对另一对组件重复该过程，直到每对组件被正确定时，以便VLSI系统又被重新定时。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式