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1. 发明申请

US20130339852A1 STREAM-BASED MEDIA MANAGEMENT 有权
标题翻译：基于流媒体的媒体管理
公开(公告)号：US20130339852A1
公开(公告)日：2013-12-19
申请号：US13524816
申请日：2012-06-15
申请人： Rajesh POORNACHANDRAN , Gyan PRAKASH , Kannan G. RAJA , John J. VALAVI
发明人： Rajesh POORNACHANDRAN , Gyan PRAKASH , Kannan G. RAJA , John J. VALAVI
IPC分类号： G06F3/048
CPC分类号： G06F3/048 , G06F3/0481 , H04N21/4312 , H04N21/44008 , H04N21/4438 , H04N21/4532 , H04N21/4782 , H04N21/4858
摘要： The present disclosure provides systems and methods for stream-based media management. A device may be configured to receive information streams including displayable content and to at least display the displayable content. For example, a stream manager in the device may be configured to control how the displayable content is displayed on a display in the device based on activity detected in the information streams. The activity may be defined by user preferences as trigger activities. For example, upon detecting a trigger activity in an information stream, the stream manager may cause the displayable content to be displayed or hidden, may cause the manner in which the displayable content is displayed (e.g., size, shape, order, etc.) to be altered, or may cause a visible or audible alert to be generated.
摘要翻译：本公开提供了用于基于流的媒体管理的系统和方法。设备可以被配置为接收包括可显示内容的信息流，并且至少显示可显示内容。例如，设备中的流管理器可以被配置为基于在信息流中检测到的活动来控制可显示内容如何在设备中的显示器上显示。活动可以由用户偏好定义为触发活动。例如，当检测到信息流中的触发活动时，流管理器可以使可显示内容被显示或隐藏，可能导致显示可显示内容的方式（例如，大小，形状，顺序等）被改变，或者可能导致产生可见或听觉警报。

2. 发明公开

US20230344864A1 Apparatus, Device, Method, and Non-Transitory Machine-Readable Storage Medium for a Node of a Blockchain Network 审中-公开
公开(公告)号：US20230344864A1
公开(公告)日：2023-10-26
申请号：US18344882
申请日：2023-06-30
申请人： Mario Jose DIVAN KOLLER , Marcos CARRANZA , Rajesh POORNACHANDRAN , Francesc GUIM BERNAT , Cesar MARTINEZ-SPESSOT
发明人： Mario Jose DIVAN KOLLER , Marcos CARRANZA , Rajesh POORNACHANDRAN , Francesc GUIM BERNAT , Cesar MARTINEZ-SPESSOT
IPC分类号： H04L9/40
CPC分类号： H04L63/1458
摘要： Various examples relate to an apparatus, device, method, and a non-transitory machine-readable storage medium for a node of a blockchain network. The apparatus comprises interface circuitry, machine-readable instructions and processor circuitry to execute the machine-readable instructions to compare a traffic pattern of requests associated with one or more smart contracts hosted by the node of the blockchain network with a reference traffic pattern, determine an estimated denial of service of at least one of the one or more smart contracts based on the comparison between the traffic pattern and the reference traffic pattern, determine one or more potential mitigations for the estimated denial of service, and apply at least one of the one or more potential mitigations.

3. 发明申请

US20210342213A1 Processing Device, Control Unit, Electronic Device, Method and Computer Program 有权
公开(公告)号：US20210342213A1
公开(公告)日：2021-11-04
申请号：US17375158
申请日：2021-07-14
申请人： Karunakara KOTARY , Toby OPFERMAN , Deepak GANDIGA SHIVAKUMAR , Vijay C. BAHIRJI , Rajesh POORNACHANDRAN
发明人： Karunakara KOTARY , Toby OPFERMAN , Deepak GANDIGA SHIVAKUMAR , Vijay C. BAHIRJI , Rajesh POORNACHANDRAN
IPC分类号： G06F11/07 , G06F9/48 , G06F9/38
摘要： A processing device is provided. The processing device comprises an interface configured to receive information about an operation state of a surrogate processor. Further, the processing device comprises a processing circuitry configured to decide whether an interrupt addressed to the processing circuitry is processed by the processing circuitry or redirected to the surrogate processing circuitry based on an operation state of the processing circuitry and the surrogate processing circuitry.

4. 发明公开

US20240231924A1 APPARATUS AND METHOD 审中-公开
公开(公告)号：US20240231924A1
公开(公告)日：2024-07-11
申请号：US18617682
申请日：2024-03-27
申请人： Sharanyan SRIKANTHAN , Karthik KUMAR , Francesc GUIM BERNAT , Rajesh POORNACHANDRAN , Marcos CARRANZA
发明人： Sharanyan SRIKANTHAN , Karthik KUMAR , Francesc GUIM BERNAT , Rajesh POORNACHANDRAN , Marcos CARRANZA
IPC分类号： G06F9/50
CPC分类号： G06F9/5027
摘要： It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions comprise instructions to identify a processing flow pattern of a large language model, LLM, wherein the LLM is executed on a processor circuitry comprising a plurality of processor cores and wherein the processing flow pattern comprising a plurality of processing phases. The machine-readable instructions further comprise instructions to identify a processing phase of the LLM from the processing flow pattern. The machine-readable instructions further comprise instructions to allocate processing resources to the processor circuitry based on the identified processing phase of the LLM.

5. 发明公开

US20240143341A1 APPARATUS, NON-TRANSITORY MACHINE-READABLE STORAGE MEDIUM, AND METHOD 审中-公开
公开(公告)号：US20240143341A1
公开(公告)日：2024-05-02
申请号：US18393790
申请日：2023-12-22
申请人： Rajesh POORNACHANDRAN , Vincent J. ZIMMER , Rajkumar KATTUR CHINNUSAMY , Mallikarjuna CHILAKALA , Sreekanth YALACHIGERE , Markus FLIERL , Brendan GREGG
发明人： Rajesh POORNACHANDRAN , Vincent J. ZIMMER , Rajkumar KATTUR CHINNUSAMY , Mallikarjuna CHILAKALA , Sreekanth YALACHIGERE , Markus FLIERL , Brendan GREGG
IPC分类号： G06F9/445
CPC分类号： G06F9/44505
摘要： It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions comprise instructions to determine one or more configurable firmware variables of a computing system based on performance analysis data of the computing system executing a workload. The machine-readable instructions further comprise instructions to set the determined one or more configurable firmware variables of the computing system based on reference data. The machine-readable instructions further comprise instructions to control the computing system to apply the set firmware variables during run-time.

6. 发明申请

US20220365813A1 Apparatus, Device, Method, and Computer Program for Scheduling an Execution of Compute Kernels 有权
公开(公告)号：US20220365813A1
公开(公告)日：2022-11-17
申请号：US17809291
申请日：2022-06-28
申请人： Rajesh POORNACHANDRAN , Ben J. ASHBAUGH , Gregory LUECK , James BRODMAN , Simon PENNYCOOK , Michael KINSNER , Roland SCHULZ
发明人： Rajesh POORNACHANDRAN , Ben J. ASHBAUGH , Gregory LUECK , James BRODMAN , Simon PENNYCOOK , Michael KINSNER , Roland SCHULZ
IPC分类号： G06F9/48
摘要： Examples relate to an apparatus, a device, a method, and a computer program for scheduling an execution of compute kernels on one or more computing devices, and to a computer system comprising such an apparatus or device. The apparatus comprises processing circuitry and interface circuitry. The processing circuitry is configured to determine an impending execution of two or more compute kernels to the one or more computing devices. The processing circuitry is configured to pipeline a data transfer related to the execution of the two or more compute kernels to the one or more computing devices via the interface circuitry.

7. 发明申请

US20160378443A1 TECHNIQUES FOR DISTRIBUTED OPERATION OF SECURE CONTROLLERS 审中-公开
标题翻译：分布式操作安全控制器的技术
公开(公告)号：US20160378443A1
公开(公告)日：2016-12-29
申请号：US14751519
申请日：2015-06-26
申请人： Mingqiu SUN , Rajesh POORNACHANDRAN , Vincent J. ZIMMER , Ned M. SMITH , Gopinatth SELVARAJE
发明人： Mingqiu SUN , Rajesh POORNACHANDRAN , Vincent J. ZIMMER , Ned M. SMITH , Gopinatth SELVARAJE
IPC分类号： G06F9/45
CPC分类号： G06F8/41 , G06F9/455 , G06F9/45516 , G06F9/45533 , G06F21/00 , G06F21/57
摘要： Various embodiments are generally directed to techniques for supporting the distributed execution of a task routine among multiple secure controllers incorporated into multiple computing devices. An apparatus includes a first processor component and first secure controller of a first computing device, where the first secure controller includes: a selection component to select the first secure controller or a second secure controller of a second computing device to compile a task routine based on a comparison of required resources to compile the task routine and available resources of the first secure controller; and a compiling component to compile the task routine into a first version of compiled routine for execution within the first secure controller by the first processor component and a second version for execution within the second secure controller by a second processor component in response to selection of the first secure controller. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及用于支持并入多个计算设备的多个安全控制器之中的任务例程的分布式执行的技术。一种装置包括第一计算设备的第一处理器组件和第一安全控制器，其中第一安全控制器包括：选择组件，用于选择第二计算设备的第一安全控制器或第二安全控制器，以基于比较所需的资源来编译任务例程和第一个安全控制器的可用资源; 以及编译组件，用于将所述任务例程编译成由所述第一处理器组件在所述第一安全控制器内执行的编译例程的第一版本，以及响应于所述第二处理器组件的选择而由所述第二处理器组件在所述第二安全控制器内执行的第二版本第一个安全控制器。描述和要求保护其他实施例。

8. 发明申请

US20220327267A1 Apparatus, Device, Method, and Computer Program for Generating Logic to be Performed by Computing Circuitry of a Computing Architecture 有权
公开(公告)号：US20220327267A1
公开(公告)日：2022-10-13
申请号：US17809293
申请日：2022-06-28
申请人： Rajesh POORNACHANDRAN , Michael KINSNER , John FREEMAN , Joseph GARVEY , Artem RADZIKHOVSKYY
发明人： Rajesh POORNACHANDRAN , Michael KINSNER , John FREEMAN , Joseph GARVEY , Artem RADZIKHOVSKYY
IPC分类号： G06F30/327 , G06F1/08 , G06F30/323 , G06F30/34 , G06F30/3312
摘要： Examples relate to an apparatus, device, method, and computer program for generating logic to be performed by computing circuitry of a computing architecture. The apparatus is configured to determine a performance-critical compute path of a compute kernel to be executed on a plurality of units of computing circuitry of a computing architecture, the compute kernel comprising a plurality of interdependent groups of computational instructions, with the performance-critical compute path being based on a subset of the interdependent groups of computational instructions. The apparatus is configured to determine, for at least one group of computational instructions outside the performance-critical compute path, a reduced clock frequency being lower than a maximally feasible clock frequency of the respective group of computational instructions. The apparatus is configured to generate logic to be performed by one or more of the plurality of separately controllable units of computing circuitry based on the compute kernel, wherein a portion of the logic that is generated to be performed by the plurality of separately controllable units of computing circuitry outside the performance-critical compute path is generated based at least in part on the reduced clock frequency.

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