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1. 发明授权

US07355207B2 Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US07355207B2
公开(公告)日：2008-04-08
申请号：US11135661
申请日：2005-05-24
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

2. 发明授权

US07763504B2 Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US07763504B2
公开(公告)日：2010-07-27
申请号：US12071186
申请日：2008-02-19
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/338
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

3. 发明申请

US20050258454A1 Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US20050258454A1
公开(公告)日：2005-11-24
申请号：US11135661
申请日：2005-05-24
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/04 , H01L21/336 , H01L27/098 , H01L27/10 , H01L29/06 , H01L29/24 , H01L29/78 , H01L29/808
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

4. 发明申请

US20080153216A1 Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US20080153216A1
公开(公告)日：2008-06-26
申请号：US12071186
申请日：2008-02-19
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/82
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

5. 发明授权

US06855981B2 Silicon carbide power device having protective diode 有权
标题翻译：具有保护二极管的碳化硅功率器件
公开(公告)号：US06855981B2
公开(公告)日：2005-02-15
申请号：US10230152
申请日：2002-08-29
申请人： Rajesh Kumar , Hiroki Nakamura , Tsuyoshi Yamamoto , Toshiyuki Morishita
发明人： Rajesh Kumar , Hiroki Nakamura , Tsuyoshi Yamamoto , Toshiyuki Morishita
IPC分类号： H01L21/04 , H01L29/24 , H01L29/66 , H01L29/808 , H01L29/861 , H01L29/866 , H01L29/872 , H01L29/76
CPC分类号： H01L29/66992 , H01L29/1608 , H01L29/66068 , H01L29/8083 , H01L29/861 , H01L29/866 , H01L29/872
摘要： A silicon carbide power device includes a junction field effect transistor and a protective diode, which is a Zener or PN junction diode. The PN junction of the protective diode has a breakdown voltage lower than the PN junction of the transistor. Another silicon carbide power device includes a protective diode, which is a Schottky diode. The Schottky diode has a breakdown voltage lower than the PN junction of the transistor by adjusting Schottky barrier height or the depletion layer formed in the semiconductor included in the Schottky diode. Another silicon carbide power device includes three protective diodes, which are Zener diodes. Two of the protective diodes are used to clamp the voltages applied to the gate and the drain of the transistor due to surge energy and used to release the surge energy. The last diode is a thermo-sensitive diode, with which the temperature of the JFET is measured.
摘要翻译：碳化硅功率器件包括结场效应晶体管和作为齐纳二极管或PN结二极管的保护二极管。保护二极管的PN结的击穿电压低于晶体管的PN结。另一种碳化硅功率器件包括一个保护二极管，它是肖特基二极管。通过调整肖特基势垒高度或肖特基二极管中包含的半导体中形成的耗尽层，肖特基二极管的击穿电压低于晶体管的PN结。另一种碳化硅功率器件包括三个保护二极管，它们是齐纳二极管。两个保护二极管用于钳位由于浪涌能量施加到晶体管的栅极和漏极的电压，并用于释放浪涌能量。最后一个二极管是热敏二极管，测量JFET的温度。

6. 发明授权

US07173284B2 Silicon carbide semiconductor device and manufacturing method 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US07173284B2
公开(公告)日：2007-02-06
申请号：US10230115
申请日：2002-08-29
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura
IPC分类号： H01L29/15
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/8083 , Y10S438/931
摘要： A silicon carbide semiconductor device that includes J-FETs has a drift layer of epitaxially grown silicon carbide having a lower impurity concentration level than a substrate on which the drift layer is formed. Trenches are formed in the surface of the drift layer, and first gate areas are formed on inner walls of the trenches. Second gate areas are formed in isolation from the first gate areas. A source area is formed on channel areas, which are located between the first and second gate areas in the drift layer. A method of manufacturing the device ensures uniform channel layer quality, which allows the device to have a normally-off characteristic, small size, and a low likelihood of defects.
摘要翻译：包括J-FET的碳化硅半导体器件具有与形成有漂移层的衬底相比杂质浓度水平低的外延生长碳化硅的漂移层。沟槽形成在漂移层的表面中，并且第一栅极区域形成在沟槽的内壁上。第二栅极区域与第一栅极区域隔离形成。源极区域形成在位于漂移层中的第一和第二栅极区域之间的沟道区域上。制造该器件的方法确保了均匀的沟道层质量，这允许器件具有常规特性，小尺寸和低缺陷可能性。

7. 发明授权

US06297100B1 Method of manufacturing silicon carbide semiconductor device using active and inactive ion species 有权
标题翻译：使用有源和非活性离子物质制造碳化硅半导体器件的方法
公开(公告)号：US06297100B1
公开(公告)日：2001-10-02
申请号：US09408185
申请日：1999-09-29
申请人： Rajesh Kumar , Masami Naito , Hiroki Nakamura , Yuichi Takeuchi
发明人： Rajesh Kumar , Masami Naito , Hiroki Nakamura , Yuichi Takeuchi
IPC分类号： H01L21336
CPC分类号： H01L29/66068 , H01L21/0445 , H01L29/0847 , H01L29/1608 , H01L29/7828 , Y10S438/931
摘要： In a vertical MOSFET, an inactive ion species is ion-implanted into a J-FET portion, a surface channel layer, and/or a base region. The inactive ion species fill intrinsic carbon vacancies or interact with interstitial Si atoms, which are possible origin or responsible for B-diffusion from the base region. Accordingly, the B-diffusion caused by the intrinsic carbon vacancies when the base region is formed is suppressed. The width of the J-FET portion is prevented from being decreased, thereby preventing an increase in resistance of the J-FET portion. Also, the conductive type of the surface channel layer is prevented from being inverted by diffused impurities.
摘要翻译：在垂直MOSFET中，将非活性离子种离子注入到J-FET部分，表面沟道层和/或基极区域中。非活性离子物质填充本征碳空位或与间隙Si原子相互作用，这是可能的起源或负责来自碱性区域的B扩散。因此，抑制了形成基极区域时由本征碳空位引起的B扩散。防止J-FET部分的宽度减小，从而防止J-FET部分的电阻增加。此外，通过扩散的杂质防止了表面通道层的导电类型的反转。

8. 发明授权

US06573534B1 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US06573534B1
公开(公告)日：2003-06-03
申请号：US09265582
申请日：1999-03-10
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Shoichi Onda , Mitsuhiro Kataoka , Kunihiko Hara , Eiichi Okuno , Jun Kojima
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Shoichi Onda , Mitsuhiro Kataoka , Kunihiko Hara , Eiichi Okuno , Jun Kojima
IPC分类号： H01L310312
CPC分类号： H01L29/7828 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/66068 , H01L29/7802 , H01L29/7838 , Y10S438/931
摘要： A semiconductor device, comprising: a semiconductor substrate comprising silicon carbide of a first conductivity type; a silicon carbide epitaxial layer of the first conductivity type; a first semiconductor region formed on the semiconductor substrate and comprising silicon carbide of a second conductivity type; a second semiconductor region formed on the first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the semiconductor substrate of the first conductivity type by the first semiconductor region; a third semiconductor region formed on the semiconductor region, connected to the semiconductor substrate and the second semiconductor region, comprising silicon carbide of the first conductivity type, and of higher resistance than the semiconductor substrate; and a gate electrode formed on the third semiconductor region via an insulating layer; wherein the third semiconductor layer is depleted when no voltage is being applied to the gate electrode so that said semiconductor device has a normally OFF characteristic.
摘要翻译：一种半导体器件，包括：包含第一导电类型的碳化硅的半导体衬底; 第一导电类型的碳化硅外延层; 形成在所述半导体衬底上并且包括第二导电类型的碳化硅的第一半导体区域; 形成在所述第一半导体区域上的第二半导体区域，包括所述第一导电类型的碳化硅并且通过所述第一半导体区域与所述第一导电类型的半导体衬底分离; 形成在所述半导体区域上的第三半导体区域，与所述半导体衬底和所述第二半导体区域连接，所述第二半导体区域包括所述第一导电型的碳化硅，并且具有比所述半导体衬底更高的电阻; 以及经由绝缘层形成在所述第三半导体区域上的栅电极; 其中当没有电压施加到所述栅电极时，所述第三半导体层被耗尽，使得所述半导体器件具有正常OFF特性。

9. 发明授权

US6057558A Silicon carbide semiconductor device and manufacturing method thereof 失效
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US6057558A
公开(公告)日：2000-05-02
申请号：US34344
申请日：1998-03-04
申请人： Tsuyoshi Yamamoto , Rajesh Kumar , Kunihiko Hara , Yuichi Takeuchi , Kazukuni Hara , Masami Naito
发明人： Tsuyoshi Yamamoto , Rajesh Kumar , Kunihiko Hara , Yuichi Takeuchi , Kazukuni Hara , Masami Naito
IPC分类号： H01L21/04 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/24 , H01L29/423 , H01L29/78 , H01L31/0312
CPC分类号： H01L29/0847 , H01L29/0626 , H01L29/42368 , H01L29/66068 , H01L29/66666 , H01L29/7828 , H01L29/045 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/4238
摘要： In a silicon carbide semiconductor device such as a trench gate type power MOSFET, the film thickness and the impurity concentration of a thin film silicon carbide semiconductor layer formed on a trench side face to constitute an accumulation-type channel-forming region and enable the device to operate with a low gate voltage, low on-resistance and low power loss are set so that on impression of a reverse bias voltage a pn junction between a P-type epitaxial layer and an n.sup.- -type epitaxial layer undergoes avalanche breakdown before the thin film silicon carbide semiconductor layer undergoes punch-through. By this means it is possible to obtain a target high source-drain withstand voltage.
摘要翻译：在诸如沟槽栅型功率MOSFET的碳化硅半导体器件中，形成在沟槽侧面上的薄膜碳化硅半导体层的膜厚度和杂质浓度构成积聚型沟道形成区域，并使器件以低栅极电压操作，设置低导通电阻和低功率损耗，使得在反向偏置电压的印象上，P型外延层和n型外延层之间的pn结在其之前经历雪崩击穿薄膜碳化硅半导体层进行穿通。通过这种方式，可以获得目标高的源极 - 漏极耐受电压。

10. 发明授权

US6054752A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US6054752A
公开(公告)日：2000-04-25
申请号：US107507
申请日：1998-06-30
申请人： Kazukuni Hara , Yuichi Takeuchi , Tsuyoshi Yamamoto , Rajesh Kumar , Mitsuhiro Kataoka
发明人： Kazukuni Hara , Yuichi Takeuchi , Tsuyoshi Yamamoto , Rajesh Kumar , Mitsuhiro Kataoka
IPC分类号： H01L21/04 , H01L29/06 , H01L29/24 , H01L29/78 , H01L29/34 , H01L29/40
CPC分类号： H01L29/7813 , H01L29/0611 , H01L29/0638 , H01L29/66068 , H01L29/7802 , H01L29/1608
摘要： A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current flowing between a source electrode and a drain electrode is formed in the semiconductor substrate. A trench is formed in a peripheral region of the unit cell to form mesa structure. A field relaxing layer is formed between an insulating film on a side face of the second trench and both the first semiconductor layer and the second semiconductor layer in order to relax concentration of an electric field in the insulating film.
摘要翻译：半导体器件包括：半导体衬底，包括形成在第一半导体层上的第一导电型第一半导体层和第二导电型第二半导体层。在半导体衬底中形成用于控制在源电极和漏电极之间流动的电流的单元。在单电池的周边区域形成沟槽，形成台面结构。在第二沟槽的侧面上的绝缘膜与第一半导体层和第二半导体层之间形成场弛豫层，以使绝缘膜中的电场的集中化。

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