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1. 发明申请

US20070266301A1 TECHNIQUES FOR GENERATING CYCLIC REDUNDANCY CHECK (CRC) VALUES 有权
标题翻译：用于生成循环冗余检查（CRC）值的技术
公开(公告)号：US20070266301A1
公开(公告)日：2007-11-15
申请号：US11382694
申请日：2006-05-10
申请人： Rajesh Bawankule , Surendra Anubolu , James Rivers , David Yen
发明人： Rajesh Bawankule , Surendra Anubolu , James Rivers , David Yen
IPC分类号： H03M13/00
CPC分类号： H03M13/093 , H03M13/09
摘要： Techniques for generating cyclic redundancy check (CRC) values are provided. Bit messages that are to be transmitted to recipients are aligned to desired byte boundaries for purposes of generating CRC values, which are to be sent with the bit messages. The CRC values are rewound or adjusted back to values associated with original lengths of the bit messages before the CRC values are transmitted or forwarded with the bit messages to recipients.
摘要翻译：提供了生成循环冗余校验（CRC）值的技术。要发送给接收者的位消息与所需的字节边界对齐，以产生要与位消息一起发送的CRC值。在将CRC值发送或使用位消息转发给接收者之前，将CRC值倒退或调整回到与位消息的原始长度相关联的值。

2. 发明授权

US07433366B1 Offered load fairness in a stack 有权
标题翻译：提供堆叠中的负载公平性
公开(公告)号：US07433366B1
公开(公告)日：2008-10-07
申请号：US10439564
申请日：2003-05-16
申请人： Surendra Anubolu , James P. Rivers , Stewart Findlater , David Hsi-Chen Yen
发明人： Surendra Anubolu , James P. Rivers , Stewart Findlater , David Hsi-Chen Yen
IPC分类号： H04L12/413 , H04L12/43 , H04L12/28 , H04J3/02
CPC分类号： H04L12/433
摘要： A technique for allocating stack bus bandwidth based on the offered load of each stack member coupled to the stacking bus allocates access opportunities to the stack bus based on the ratio of the offered loads of the coupled stack members.
摘要翻译：基于耦合到堆叠总线的每个堆叠构件的提供的负载分配堆叠总线带宽的技术基于所提供的耦合堆叠构件的负载的比率来分配对堆栈总线的访问机会。

3. 发明申请

US20110194426A1 HIERARCHICAL QUEUING AND SCHEDULING 审中-公开
标题翻译：分层排队和调度
公开(公告)号：US20110194426A1
公开(公告)日：2011-08-11
申请号：US12702826
申请日：2010-02-09
申请人： Chien FANG , Hiroshi Suzuki , Rong Pan , Abhijit Kumar Choudhury , David Sheldon Stephenson , Surendra Anubolu , Hariprasad R. Ginjpalli , Stanley WaiYip Ho , Peter Geoffrey Jones
发明人： Chien FANG , Hiroshi Suzuki , Rong Pan , Abhijit Kumar Choudhury , David Sheldon Stephenson , Surendra Anubolu , Hariprasad R. Ginjpalli , Stanley WaiYip Ho , Peter Geoffrey Jones
IPC分类号： H04L12/56
CPC分类号： H04L47/20 , H04L47/32 , H04L47/52 , H04L47/60 , H04L49/90
摘要： In an example embodiment, there is disclosed herein logic encoded in at least one tangible media for execution and when executed operable to receive a packet. The logic determines a client associated with the packet. The client associated with a service set, and the service set associated with a transmitter. The logic determines a drop probability for the selected client determines a current packet arrival rate for the selected client and determines whether to enqueue or drop the packet based on the drop probability for the selected client and the current packet arrival rate associated with the selected client. The drop probability is based on a packet arrival rate and virtual queue length for the, which is based on a packet arrival rate and virtual queue length for the service set that is based on a packet arrival rate and virtual queue length for the transmitter.
摘要翻译：在一个示例性实施例中，本文公开了逻辑编码在至少一个有形介质中用于执行，并且当被执行时可操作以接收分组。逻辑确定与数据包相关联的客户端。与服务集相关联的客户端以及与发射机相关联的服务集合。该逻辑确定所选择的客户端的丢弃概率确定所选择的客户端的当前分组到达速率，并且基于所选客户端的丢弃概率以及与所选择的客户端相关联的当前分组到达速率，确定是否对分组进行入队或丢弃。丢弃概率基于分组到达速率和虚拟队列长度，其基于基于分组到达速率和发射机的虚拟队列长度的服务集合的分组到达速率和虚拟队列长度。

4. 发明授权

US06240475B1 Timer based arbitrations scheme for a PCI multi-function device 失效
标题翻译：用于PCI多功能设备的基于定时器的仲裁方案
公开(公告)号：US06240475B1
公开(公告)日：2001-05-29
申请号：US09001245
申请日：1997-12-30
申请人： Surendra Anubolu
发明人： Surendra Anubolu
IPC分类号： G06F1314
CPC分类号： G06F13/372
摘要： According to the present invention, a function timer is started whenever the PCI bus is granted to the function that did not access the PCI bus prior to the last bus idle state. The timer counts down to zero and waits until another function requests the PCI bus. During the time the timer is not zero, the current function will have the highest priority. Even if a PCI bus disconnect signal or retry signal forces the current function to deassert the request signal and start the request again, the current function is guaranteed to win the arbitration among the multiple contenders within the multi-function device. Since during the time slot, the same function will the granted access to the PCI bus, the next request will most likely be readily available from the PCI bridge's buffer which has additional data stored in anticipation for the next request. The use of the PCI bridge's buffer will maximize the system memory bus usage while increasing the PCI bus throughput. The time slot based arbitration according to the present invention rotates the priority to the other requesting function after the predetermined time expires which limits the latency for all the functions.
摘要翻译：根据本发明，每当PCI总线被授予在最后一个总线空闲状态之前未访问PCI总线的功能时，功能定时器就被启动。定时器倒计时到零，等待直到另一个功能请求PCI总线。在定时器不为零的时间内，当前功能将具有最高优先级。即使PCI总线断开信号或重试信号强制当前功能来解除请求信号并再次启动请求，则保证当前功能在多功能设备内的多个竞争者之间赢得仲裁。由于在时隙期间，相同的功能将允许访问PCI总线，所以下一个请求将很有可能从PCI桥的缓冲区中获得，该缓冲区具有存储在预期下一个请求中的附加数据。使用PCI桥的缓冲区可以最大化系统内存总线的使用，同时增加PCI总线的吞吐量。根据本发明的基于时隙的仲裁在预定时间到期之后将优先级转到另一个请求功能，这限制了所有功能的等待时间。

5. 发明授权

US07634712B2 Techniques for generating cyclic redundancy check (CRC) values 有权
标题翻译：用于生成循环冗余校验（CRC）值的技术
公开(公告)号：US07634712B2
公开(公告)日：2009-12-15
申请号：US11382694
申请日：2006-05-10
申请人： Rajesh Ekras Bawankule , Surendra Anubolu , James Paul Rivers , David Hsi-Chen Yen
发明人： Rajesh Ekras Bawankule , Surendra Anubolu , James Paul Rivers , David Hsi-Chen Yen
IPC分类号： H03M13/00
CPC分类号： H03M13/093 , H03M13/09
摘要： Techniques for generating cyclic redundancy check (CRC) values are provided. Bit messages that are to be transmitted to recipients are aligned to desired byte boundaries for purposes of generating CRC values, which are to be sent with the bit messages. The CRC values are rewound or adjusted back to values associated with original lengths of the bit messages before the CRC values are transmitted or forwarded with the bit messages to recipients.
摘要翻译：提供了生成循环冗余校验（CRC）值的技术。要发送给接收者的位消息与所需的字节边界对齐，以产生要与位消息一起发送的CRC值。在将CRC值发送或使用位消息转发给接收者之前，将CRC值倒退或调整回到与位消息的原始长度相关联的值。

6. 发明授权

US07523227B1 Interchangeable standard port or stack port 有权
标题翻译：可互换的标准端口或堆叠端口
公开(公告)号：US07523227B1
公开(公告)日：2009-04-21
申请号：US10345435
申请日：2003-01-14
申请人： Charles T. Yager , Surendra Anubolu , Sandeep Arvind Patel , Paul Booth , Amar C. Amar , Bradley D. Erickson
发明人： Charles T. Yager , Surendra Anubolu , Sandeep Arvind Patel , Paul Booth , Amar C. Amar , Bradley D. Erickson
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： An Interchangeable Standard Port or Stack Port (ISPSP) uses a standard physical connector such as an RJ-45 or SFP. The ISPSP automatically detects whether it is connected to a standard port, such as a 1000BaseT, or whether it is connected to another ISPSP stacking port. This automatic detection can be done through hardware or software. Once the auto-detection is complete the routing platform will automatically configure the ISPSP port for standard 1 Gbps bit rate and framing, or for stacking, e.g., 2.5 Gbps bit rate, and framing.
摘要翻译：可互换标准端口或堆叠端口（ISPSP）使用标准物理连接器，如RJ-45或SFP。 ISPSP自动检测是否连接到标准端口，如1000BaseT，或者是否连接到另一个ISPSP堆叠端口。这种自动检测可以通过硬件或软件完成。一旦自动检测完成，路由平台将自动配置ISPSP端口，用于标准1 Gbps比特率和成帧，或用于堆叠，例如2.5 Gbps比特率和成帧。

7. 发明授权

US07277910B1 System and method for balancing rings coupling routing platforms 有权
标题翻译：用于平衡环耦合路由平台的系统和方法
公开(公告)号：US07277910B1
公开(公告)日：2007-10-02
申请号：US10441487
申请日：2003-05-20
申请人： Surendra Anubolu , James P. Rivers , Stewart Findlater
发明人： Surendra Anubolu , James P. Rivers , Stewart Findlater
IPC分类号： G06F15/16 , H04L12/42 , H04L12/403
CPC分类号： H04L12/433
摘要： A ring access system, for use in system having a plurality of routing platforms coupled by redundant rings, that allows access to either ring when a token is received at a first ring if all outstanding locally-sourced data has been stripped from the second ring.
摘要翻译：环路接入系统，用于具有由冗余环耦合的多个路由平台的系统的系统，当所有优先的本地来源的数据已经从第二环被剥离时，允许在第一环接收到令牌时访问任一个环。

8. 发明授权

US5948076A Method and system for changing peripheral component interconnect configuration registers 失效
标题翻译：用于改变外设组件互连配置寄存器的方法和系统
公开(公告)号：US5948076A
公开(公告)日：1999-09-07
申请号：US1615
申请日：1997-12-31
申请人： Surendra Anubolu , Samuel C. M. Chih , Jacqueline Irene Humfeld
发明人： Surendra Anubolu , Samuel C. M. Chih , Jacqueline Irene Humfeld
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4063
摘要： The present invention provides the new capability to change PCI configuration registers. For example, the present invention allows programs, such as operating systems and device drivers, which are typically programmed to only look to the device ID, without looking to the subsystem ID, to read the subsystem ID when appropriate. If the programs do not read the subsystem ID register, then when appropriate, the full or partial content of the subsystem ID is copied into the device ID register.
摘要翻译：本发明提供了改变PCI配置寄存器的新功能。例如，本发明允许诸如操作系统和设备驱动程序的程序通常被编程为仅在不考虑子系统ID的情况下查看设备ID以在适当时读取子系统ID。如果程序没有读取子系统ID寄存器，则在合适的情况下，将子系统ID的全部或部分内容复制到设备ID寄存器中。

9. 发明授权

US5913924A Use of a stored signal to switch between memory banks 失效
标题翻译：使用存储的信号在存储体之间切换
公开(公告)号：US5913924A
公开(公告)日：1999-06-22
申请号：US574534
申请日：1995-12-19
申请人： Jianyun Zhou , Surendra Anubolu
发明人： Jianyun Zhou , Surendra Anubolu
IPC分类号： G06F12/06 , G06F13/14 , G06F13/00
CPC分类号： G06F12/0653 , G06F12/0615 , G06F13/14
摘要： A computer system includes a number of storage elements encoded with space selection instructions and at least one current-space storage element that together allow a computer to address a larger number of devices than allowed by a limited number of address terminals on the computer. Specifically, the current-space storage element is encoded with a space-selection signal that indicates a "current" address space, i.e. which one of a number of mutually exclusive address spaces is currently accessed. The space-selection signal can be changed by any device using a data bus to store signals indicative of a new address space as the "current" address space in the current-space storage element. The current-space storage element is included in a first device that can be accessed by the computer at any time by driving a signal active on a high address line of an address bus. When the signal on the high address line is inactive, the computer accesses one of a number of second devices that are located in mutually exclusive address spaces, as indicated by the current-space storage element's signal.
摘要翻译：计算机系统包括用空间选择指令编码的多个存储元件和至少一个当前空间存储元件，其一起允许计算机寻址比计算机上的有限数量的地址终端允许的更多数量的设备。具体地，当前空间存储元件用指示“当前”地址空间的空间选择信号进行编码，即当前访问多个互斥地址空间中的哪一个。空间选择信号可以由使用数据总线的任何设备改变，以存储指示新地址空间的信号作为当前空间存储元件中的“当前”地址空间。当前空间存储元件包括在第一设备中，可以随时通过驱动在地址总线的高地址线上激活的信号由计算机访问。当高地址线上的信号不活动时，计算机访问位于互斥地址空间中的多个第二设备中的一个，如当前空间存储元件的信号所示。

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