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    • 4. 发明授权
      US08307136B2 Data movement system and method 有权
    • Data movement system and method
    • 数据移动系统及方法
    • US08307136B2
    • 2012-11-06
    • US12534492
    • 2009-08-03
    • Neil S. Feiereisel , Glen O. Sescila, III , Craig M. Conway , Brian Keith Odom , M. Dean Brockhausen, Jr.
    • Neil S. Feiereisel , Glen O. Sescila, III , Craig M. Conway , Brian Keith Odom , M. Dean Brockhausen, Jr.
    • G06F13/00
    • G06F13/385 , G06F2213/0026
    • Provided is a method of streaming transfer of data between a plurality of devices of a computer system. The method includes providing data to be sent from a source device to a target device and includes receiving, at the source device, one or more transfer credits from the target device. A transfer credit may be indicative of an amount of data that the target device is authorizing to be sent to the target device. The method also includes determining whether or not an accumulated transfer credit value satisfies a threshold value. If the accumulated transfer credit value satisfies the threshold value, the source device sends data to the target device and modifies the accumulated transfer credit value based on a quantity of data sent. If the accumulated transfer credit value does not satisfy the threshold value the source device does not send data to the target device.
    • 提供了一种在计算机系统的多个设备之间流传输数据的方法。 该方法包括提供要从源设备发送到目标设备的数据，并且包括在源设备处从目标设备接收一个或多个传送信用。 转移信用可以指示目标设备授权发送到目标设备的数据量。 该方法还包括确定累积的转移信用值是否满足阈值。 如果积累的转移信用值满足阈值，则源设备将数据发送到目标设备，并根据发送的数据量来修改累计转账信用值。 如果累积的转移信用值不满足阈值，则源设备不向目标设备发送数据。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5875313A PCI bus to IEEE 1394 bus translator employing write pipe-lining and sequential write combining 失效
    • PCI bus to IEEE 1394 bus translator employing write pipe-lining and sequential write combining
    • US5875313A
    • 1999-02-23
    • US826920
    • 1997-04-08
    • Glen O. Sescila, III , Brian K. Odom , Kevin L. Schultz
    • Glen O. Sescila, III , Brian K. Odom , Kevin L. Schultz
    • G06F13/40 , H04L12/40 , H04L12/64 , G06F13/00
    • H04L12/40123 , G06F13/4059
    • A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer. The translator, if configured to a first mode, pipelines subsequent PCI bus write cycles by posting the PCI write cycle data into the write-posting FIFO once reception of the first 1394 write request packet has been acknowledged by the host computer but prior to the host computer responding with status indicating the completion of the write transaction, in particular whether or not a resource conflict occurred. In response to a PCI read cycle initiated by the PCI device, the translator pre-fetches a larger amount of data than specified in the PCI read cycle from the host computer into a pre-fetch FIFO in order to satisfy subsequent PCI read cycles which are in address sequence with the previous PCI read cycle. The translator pre-fetches more data from the host computer once the pre-fetch FIFO becomes a predetermined amount empty in order to pipeline the consumption of the pre-fetch data by the PCI device and the transmission of the pre-fetch data by the host computer to the translator.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明申请
      US20090100201A1 Optimizing the Responsiveness and Throughput of a System Performing Packetized Data Transfers 有权
    • Optimizing the Responsiveness and Throughput of a System Performing Packetized Data Transfers
    • 优化执行分组化数据传输的系统的响应性和吞吐量
    • US20090100201A1
    • 2009-04-16
    • US12341438
    • 2008-12-22
    • Andrew B. Moch , Aaron T. Rossetto , Brent C. Schwan , Glen O. Sescila, III
    • Andrew B. Moch , Aaron T. Rossetto , Brent C. Schwan , Glen O. Sescila, III
    • G06F3/00
    • H04L1/24 , H04L43/50 , H04L2001/0094
    • A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.
    • 一种用于在包括发送和接收设备的系统中管理分组化数据传输的机制。 发送设备可以以多个分组向接收设备发送数据，每个分组具有预定数量的数据字节宽。 发送装置可以包括传送计数单元，用于基于发送的数据字节的数量维持数据传送计数。 接收设备可以使用传输计数标记对发送设备进行编程，该传送计数标记可以是对应于数据传送计数的特定计数的数字。 发送装置可以计算数据传送计数和传送计数标记之间的差异。 如果传送计数和传送计数标记之间的差小于预定数量，则发送装置可以向接收装置发送具有小于预定数量的数据字节的短数据包。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US5937175A PCI bus to IEEE 1394 bus translator employing pipe-lined read prefetching 失效
    • PCI bus to IEEE 1394 bus translator employing pipe-lined read prefetching
    • US5937175A
    • 1999-08-10
    • US826925
    • 1997-04-08
    • Glen O. Sescila, III , Brian K. Odom , Kevin L. Schultz
    • Glen O. Sescila, III , Brian K. Odom , Kevin L. Schultz
    • G06F13/12 , G06F13/40 , H04L12/40 , H04L12/64 , G06F13/38
    • H04L12/40123 , G06F13/128 , G06F13/4059
    • A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer. The translator, if configured to a first mode, pipelines subsequent PCI bus write cycles by posting the PCI write cycle data into the write-posting FIFO once reception of the first 1394 write request packet has been acknowledged by the host computer but prior to the host computer responding with status indicating the completion of the write transaction, in particular whether or not a resource conflict occurred. In response to a PCI read cycle initiated by the PCI device, the translator pre-fetches a larger amount of data than specified in the PCI read cycle from the host computer into a pre-fetch FIFO in order to satisfy subsequent PCI read cycles which are in address sequence with the previous PCI read cycle. The translator pre-fetches more data from the host computer once the pre-fetch FIFO becomes a predetermined amount empty in order to pipeline the consumption of the pre-fetch data by the PCI device and the transmission of the pre-fetch data by the host computer to the translator.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US07849210B2 Optimizing the responsiveness and throughput of a system performing packetized data transfers 有权
    • Optimizing the responsiveness and throughput of a system performing packetized data transfers
    • 优化执行分组化数据传输的系统的响应性和吞吐量
    • US07849210B2
    • 2010-12-07
    • US12341438
    • 2008-12-22
    • Andrew B. Moch , Aaron T. Rossetto , Brent C. Schwan , Glen O. Sescila, III
    • Andrew B. Moch , Aaron T. Rossetto , Brent C. Schwan , Glen O. Sescila, III
    • G06F15/16
    • H04L1/24 , H04L43/50 , H04L2001/0094
    • A mechanism for managing packetized data transfers in a system including a transmitting and a receiving device. The transmitting device may transmit data to the receiving device in a plurality of packets, each packet a predetermined number of data bytes wide. The transmitting device may include a transfer count unit to maintain a data transfer count based on a number of transmitted data bytes. The receiving device may program the transmitting device with a transfer count mark, which may be a number that corresponds to a specific count of the data transfer count. The transmitting device may calculate a difference between the data transfer count and the transfer count mark. If the difference between the transfer count and the transfer count mark is less than the predetermined number, the transmitting device may transmit a short data packet having less than the predetermined number of data bytes to the receiving device.
    • 一种用于在包括发送和接收设备的系统中管理分组化数据传输的机制。 发送设备可以以多个分组向接收设备发送数据，每个分组具有预定数量的数据字节宽。 发送装置可以包括传送计数单元，用于基于发送的数据字节的数量维持数据传送计数。 接收设备可以使用传输计数标记对发送设备进行编程，该传送计数标记可以是对应于数据传送计数的特定计数的数字。 发送装置可以计算数据传送计数和传送计数标记之间的差异。 如果传送计数和传送计数标记之间的差小于预定数量，则发送装置可以向接收装置发送具有小于预定数量的数据字节的短数据包。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US5953511A PCI bus to IEEE 1394 bus translator 失效
    • PCI bus to IEEE 1394 bus translator
    • US5953511A
    • 1999-09-14
    • US835527
    • 1997-04-08
    • Glen O. Sescila, III , Brian K. Odom , Kevin L. Schultz
    • Glen O. Sescila, III , Brian K. Odom , Kevin L. Schultz
    • G06F13/40 , H04L12/40 , H04L12/64 , G06F13/38 , G06F13/00
    • H04L12/40123 , G06F13/4027 , G06F13/404 , G06F13/4059
    • A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer. The translator, if configured to a first mode, pipelines subsequent PCI bus write cycles by posting the PCI write cycle data into the write-posting FIFO once reception of the first 1394 write request packet has been acknowledged by the host computer but prior to the host computer responding with status indicating the completion of the write transaction, in particular whether or not a resource conflict occurred. In response to a PCI read cycle initiated by the PCI device, the translator pre-fetches a larger amount of data than specified in the PCI read cycle from the host computer into a pre-fetch FIFO in order to satisfy subsequent PCI read cycles which are in address sequence with the previous PCI read cycle. The translator pre-fetches more data from the host computer once the pre-fetch FIFO becomes a predetermined amount empty in order to pipeline the consumption of the pre-fetch data by the PCI device and the transmission of the pre-fetch data by the host computer to the translator.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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