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1. 发明授权

US07659169B2 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07659169B2
公开(公告)日：2010-02-09
申请号：US11574341
申请日：2005-08-10
申请人： Radu Surdeanu , Erwin Hijzen , Michael Antoine Zandt , Raymond Josephus Hueting
发明人： Radu Surdeanu , Erwin Hijzen , Michael Antoine Zandt , Raymond Josephus Hueting
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： There is a method of manufacturing a semiconductor device with a dual gate field effect transistor, the method including a semiconductor body a semiconductor material having a surface with a source region and a drain region of a first conductivity type and with a channel region of a second conductivity type opposite to the first conductivity type between the source region and the drain region and with a first gate region separated from the surface of the semiconductor body by a first gate dielectric above the channel region and with a second gate region situated opposite to the first gate region and formed within a recess in an opposite surface of the semiconductor body so as to be separated from the channel region by a second gate dielectric wherein the recess is formed with a local change of the doping of the channel region and by etching starting from the opposite surface of the semiconductor body.
摘要翻译：存在制造具有双栅场效应晶体管的半导体器件的方法，该方法包括：半导体本体，具有具有第一导电类型的源极区和漏极区的表面的半导体材料，以及具有第二导电类型的沟道区导电类型与源极区域和漏极区域之间的第一导电类型相反，并且具有通过沟道区域上方的第一栅极电介质与半导体本体的表面分离的第一栅极区域以及与第一栅极区域相对的第一栅极区域并且形成在半导体主体的相对表面中的凹部内，以便通过第二栅极电介质与沟道区分离，其中凹部形成有沟道区域的掺杂的局部变化，并且通过从半导体本体的相对表面。

2. 发明申请

US20080194069A1 Method of Manufacturing a Semiconductor Device and Semiconductor Device Obtained With Such a Method 有权
标题翻译：制造使用这种方法获得的半导体器件和半导体器件的方法
公开(公告)号：US20080194069A1
公开(公告)日：2008-08-14
申请号：US11574341
申请日：2005-08-10
申请人： Radu Surdeanu , Erwin Hijzen , Michael Antoine Zandt , Raymond Josephus Hueting
发明人： Radu Surdeanu , Erwin Hijzen , Michael Antoine Zandt , Raymond Josephus Hueting
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/78648
摘要： The invention relates to a method of manufacturing a semiconductor device (1.0) with a dual gate field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type and with a channel region (4) of a second conductivity type opposite to the first conductivity type between the source region (2) and the drain region (3) and with a first gate region (5) separated from the surface of the semiconductor body by a first gate dielectric (6) above the channel region (4) and with a second gate region (7) situated opposite to the first gate region (5) and formed within a recess (20) in an opposite surface of the semiconductor body (1) so as to be separated from the channel region (4) by a second gate dielectric (8), wherein the recess (20) is formed by means of a local change of the doping (9) of the channel region (4) and by performing an etching step starting from the opposite surface of the semiconductor body (1).
摘要翻译：本发明涉及一种制造具有双栅场效应晶体管的半导体器件（1.0）的方法，其中半导体材料的半导体本体（1）的表面设置有源区（2）和漏极区域（3）和与源极区域（2）和漏极区域（3）之间的第一导电类型相反的第二导电类型的沟道区域（4）和第一栅极区域（ 5）通过沟道区域（4）上方的第一栅极电介质（6）和与第一栅极区域（5）相对并形成在凹槽内的第二栅极区域（7）与半导体本体的表面分离 20）在半导体本体（1）的相对表面中，以便通过第二栅极电介质（8）与沟道区（4）分离，其中凹部（20）通过通道区域（4）的掺杂（9）和从半导体本体（1）的相对表面开始蚀刻步骤。

3. 发明授权

US08772073B2 Integrated circuit manufacturing method 有权
标题翻译：集成电路制造方法
公开(公告)号：US08772073B2
公开(公告)日：2014-07-08
申请号：US12988110
申请日：2009-04-14
申请人： Viet Nguyen Hoang , Radu Surdeanu , Benoit Bataillou
发明人： Viet Nguyen Hoang , Radu Surdeanu , Benoit Bataillou
IPC分类号： H01L21/00 , H01L27/146 , H01L21/3105
CPC分类号： H01L27/14685 , H01L21/31053 , H01L21/31111 , H01L27/14621 , H01L27/14629
摘要： A method of providing a dielectric material (18) having regions (18′, 18″) with a varying thickness in an IC manufacturing process is disclosed. The method comprises forming a plurality of patterns in respective regions (20′, 20″) of the dielectric material (18), each pattern increasing the susceptibility of the dielectric material (18) to a dielectric material removal step by a predefined amount and exposing the dielectric material (18) to the dielectric material removal step. In an embodiment, the IC comprises a plurality of pixilated elements (12) and a plurality of light interference elements (24), each comprising a first mirror element (16) and a second mirror element (22), a region of the dielectric material (18) separating the first mirror element (16) and the second element (22), and each being arranged over one of said pixilated elements (12), the method further comprising forming the respective first mirror elements (16) in a dielectric layer (14) over a substrate (10) comprising the plurality of pixilated elements; depositing the dielectric material over the dielectric layer; and forming the respective second mirror elements such that each second mirror element is separated from a respective first mirror element by a region of the exposed dielectric material. Hence, an IC having a layer of a dielectric material (18) comprising regions of different thicknesses can be obtained requiring only a few process steps.
摘要翻译：公开了一种在IC制造过程中提供具有变化厚度的区域（18'，18“）的介电材料（18）的方法。该方法包括在介电材料（18）的相应区域（20'，20“）中形成多个图案，每个图案将电介质材料（18）的敏感性增加到电介质材料去除步骤预定量并暴露介电材料（18）到介电材料去除步骤。在一个实施例中，IC包括多个像素化元件（12）和多个光干涉元件（24），每个元件包括第一镜元件（16）和第二镜元件（22），介电材料的区域（18）分离第一镜元件（16）和第二元件（22），并且每个被布置在一个所述像素化元件（12）上，所述方法还包括在电介质层中形成相应的第一镜元件（16）（14）包括多个像素化元件的衬底（10）上; 在电介质层上沉积电介质材料; 以及形成各个第二反射镜元件，使得每个第二反射镜元件通过暴露的电介质材料的区域与相应的第一反射镜元件分离。因此，可以获得具有包括不同厚度的区域的电介质材料层（18）的IC，只需要几个工艺步骤。

4. 发明授权

US08723443B2 Method of controlling an LED, and an LED controller 有权
标题翻译：控制LED的方法和LED控制器
公开(公告)号：US08723443B2
公开(公告)日：2014-05-13
申请号：US13257266
申请日：2010-02-25
申请人： Peter Hubertus Franciscus Deurenberg , Gert-Jan Koolen , Gian Hoogzaad , Radu Surdeanu , Pascal Bancken , Benoit Bataillou , Viet Nguyen Hoang
发明人： Peter Hubertus Franciscus Deurenberg , Gert-Jan Koolen , Gian Hoogzaad , Radu Surdeanu , Pascal Bancken , Benoit Bataillou , Viet Nguyen Hoang
IPC分类号： H05B33/00
CPC分类号： H05B33/086 , H05B33/0815 , H05B33/0848
摘要： A method is disclosed of controlling a LED, comprising driving the LED with a DC current for a first time, interrupting the DC current for a second time such that the first time and the second time sum to a period, determining at least one characteristic of the LED while the DC current is interrupted, and controlling the DC current during a subsequent period in dependence on the at least one characteristic. The invention thus benefits from the simplicity of DC operation. By operating at the LED in a DC mode, rather than say in a PWM mode, the requirement to be able to adjust the duty cycle is avoided. By including interruptions to the DC current, it is possible to utilize the LED itself to act as a sensor in order to determine a characteristic of the LED. The need for additional sensors is thereby avoided.
摘要翻译：公开了一种控制LED的方法，包括第一次用DC电流驱动LED，第二次中断DC电流，使得第一时间和第二时间总和到一个周期，确定至少一个特性所述LED在DC电流中断期间，并且根据所述至少一个特性在随后的时段期间控制所述DC电流。因此，本发明由于DC操作的简单性而受益。通过在DC模式下操作LED，而不是在PWM模式下说明，可以避免能够调整占空比的要求。通过包含直流电流的中断，可以利用LED本身作为传感器，以便确定LED的特性。从而避免了对附加传感器的需要。

5. 发明授权

US07897469B2 Impact ionization MOSFET method 失效
标题翻译：冲击电离MOSFET法
公开(公告)号：US07897469B2
公开(公告)日：2011-03-01
申请号：US12521963
申请日：2007-12-12
申请人： Radu Surdeanu
发明人： Radu Surdeanu
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/66356 , H01L29/66659 , H01L29/7391
摘要： A method of manufacturing an I-MOS device includes forming a semiconductor layer (2) on a buried insulating layer (4). A gate structure (23) including a gate stack (14) is formed on the semiconductor layer, and used to (5) self align the formation of a source region (28) by implantation. Then, an etch step is used to selectively etch the gate structure (23) and this is followed by forming a drain region (36) by implantation. The method can precisely control the i-region length (38) between source region (28) and gate stack (14).
摘要翻译：一种制造I-MOS器件的方法包括在掩埋绝缘层（4）上形成半导体层（2）。在半导体层上形成包括栅叠层（14）的栅结构（23），用于（5）通过注入自对准源极区（28）的形成。然后，使用蚀刻步骤来选择性地蚀刻栅极结构（23），然后通过注入形成漏极区域（36）。该方法可以精确控制源极区域（28）和栅极叠层（14）之间的i区域长度（38）。

6. 发明申请

US20100314684A1 FINFET WITH SEPARATE GATES AND METHOD FOR FABRICATING A FINFET WITH SEPARATE GATES 有权
标题翻译：具有分离栅的FINFET和用于制造具有独立栅的FINFET的方法
公开(公告)号：US20100314684A1
公开(公告)日：2010-12-16
申请号：US12866852
申请日：2009-02-09
申请人： Jan Sonsky , Radu Surdeanu
发明人： Jan Sonsky , Radu Surdeanu
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7856
摘要： The present invention relates to a FinFET with separate gates and to a method for fabricating the same. A dielectric gate-separation layer between first and second gate electrodes has an extension in a direction pointing from a first to a second gate layer that is smaller than a lateral extension of the fin between its opposite lateral faces. This structure corresponds with a processing method that starts from a covered basic FinFET structure with a continuous first gate layer, and proceeds to remove parts of the first gate layer and of a first gate-isolation layer through a contact opening to the gate layer. Subsequently, a replacement gate-isolation layer that at the same time forms the gate separation layer fabricated, followed by filling the tunnel with a replacement gate layer and a metal filling.
摘要翻译：本发明涉及具有分离栅极的FinFET及其制造方法。在第一和第二栅电极之间的电介质栅极分隔层在从第一栅极层到第二栅极层的方向上具有小于翅片在其相对侧面之间的横向延伸的方向上的延伸。该结构对应于从具有连续的第一栅极层的覆盖的基本FinFET结构开始的处理方法，并且通过到栅极层的接触开口去除第一栅极层和第一栅极隔离层的部分。随后，替代栅极隔离层同时形成栅极分离层，随后用替换栅极层和金属填充物填充隧道。

7. 发明授权

US07838368B2 Nanoscale fet 有权
标题翻译：纳米级
公开(公告)号：US07838368B2
公开(公告)日：2010-11-23
申请号：US11632738
申请日：2005-07-12
申请人： Radu Surdeanu , Prabhat Agarwal , Abraham Rudolf Balkenende , Erik P. A. M. Bakkers
发明人： Radu Surdeanu , Prabhat Agarwal , Abraham Rudolf Balkenende , Erik P. A. M. Bakkers
IPC分类号： H01L21/336 , H01L29/775
CPC分类号： H01L29/78 , B82Y10/00 , B82Y40/00 , H01L29/0665 , H01L29/0673 , H01L29/20 , H01L29/76 , Y10S438/962 , Y10S977/762 , Y10S977/818 , Y10S977/938
摘要： A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source (20) and drain (26) regions are formed of nanowire ania the channel region (24) is in the form of a nanotube. An insulated gate (32) is provided adjacent to the channel region (24) for controlling conduction i ni the channel region between the source and drain regions.
摘要翻译：晶体管器件由具有源极区，漏极区和源极和漏极区之间的沟道区的连续线性纳米结构形成。源极（20）和漏极（26）区域由纳米线形成，沟道区域（24）呈纳米管形式。绝缘栅极（32）设置成邻近沟道区（24），用于控制源极和漏极区之间的沟道区。

8. 发明申请

US20090242987A1 DOUBLE-GATE SEMICONDUCTOR DEVICES HAVING GATES WITH DIFFERENT WORK FUNCTIONS AND METHODS OF MANUFACTURE THEREOF 有权
标题翻译：具有不同工作功能的门的双栅半导体器件及其制造方法
公开(公告)号：US20090242987A1
公开(公告)日：2009-10-01
申请号：US12278629
申请日：2007-02-02
申请人： Mark Van Dal , Radu Surdeanu
发明人： Mark Van Dal , Radu Surdeanu
IPC分类号： H01L27/12 , H01L21/762 , H01L21/20
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/42384 , H01L29/4908 , H01L29/7856
摘要： A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the first gate facing the fin being formed of polycrystalline silicon, and at least a portion of the second gate facing the fin being formed of a metal suicide compound. The different compositions of the two gates provide different respective work functions to reduce short channel effects.
摘要翻译：提供了双栅FinFET及其制造方法。 FinFET包括与翅片（20）的相应侧面相邻的第一和第二栅极（72,74），其中第一栅极的面对鳍片的至少一部分由多晶硅形成，并且第二栅极的至少一部分面向翅片由金属硅化物形成。两个门的不同组成提供不同的各自的功能来减少短路效应。

9. 发明申请

US20080318375A1 Method of Fabricating a Duel-Gate Fet 有权
标题翻译：制造决斗门的方法
公开(公告)号：US20080318375A1
公开(公告)日：2008-12-25
申请号：US11815100
申请日：2006-01-23
申请人： Wibo Daniel Van Noort , Franciscus Petrus Widdershoven , Radu Surdeanu
发明人： Wibo Daniel Van Noort , Franciscus Petrus Widdershoven , Radu Surdeanu
IPC分类号： H01L21/8238
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7854
摘要： The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion (2) on a substrate (1), a first layer (3) and a second layer (4) are formed, after which the top surface of the protrusion (2) is exposed. A portion of the first layer (3) is selectively removed relative to the protrusion (2) and the second layer (4), thereby creating a fin (6) and a trench (5). Also a method is presented to form a plurality of fins (6) and trenches (5). The dual-gate FET is created by forming a gate electrode (7) in the trench(es) (5) and a source and drain region. Further a method is presented to fabricate an extremely short-length asymmetric dual-gate FET with two gate electrodes that can be biased separately.
摘要翻译：本发明提供了一种使用常规半导体处理技术制造极短的双栅极FET的方法，其具有非常小且可重现的鳍，其间距和宽度都小于可以用光刻技术获得的。在基板（1）上的突起（2）上形成第一层（3）和第二层（4），然后露出突起（2）的上表面。相对于突起（2）和第二层（4），第一层（3）的一部分被选择性地去除，从而形成翅片（6）和沟槽（5）。还提出了形成多个翅片（6）和沟槽（5）的方法。通过在沟槽（5）中形成栅电极（7）和源极和漏极区域来产生双栅极FET。此外，提出了一种制造具有可分别偏置的两个栅电极的极短的非对称双栅极FET的方法。

10. 发明授权

US08368105B2 Manufacturing method and integrated circuit having a light path to a pixilated element 有权
标题翻译：具有到像素化元件的光路的制造方法和集成电路
公开(公告)号：US08368105B2
公开(公告)日：2013-02-05
申请号：US12922072
申请日：2009-03-09
申请人： Viet Nguyen Hoang , Radu Surdeanu , Benoit Bataillou
发明人： Viet Nguyen Hoang , Radu Surdeanu , Benoit Bataillou
IPC分类号： H01L33/00
CPC分类号： H01L27/14625 , H01L27/14621 , H01L27/14636 , H01L27/14685
摘要： The present invention relates to a manufacturing method of an integrated circuit (IC) comprising a substrate (10) comprising a pixelated element (12) and a light path (38) to the pixelated element (12). The IC comprises a first dielectric layer (14) covering the substrate (10) but not the pixilated element (12), a first metal layer (16) covering a part of the first dielectric layer (14), a second dielectric layer (18) covering a further part of first dielectric layer (14), a second metal layer (20) covering a part of the second dielectric layer (18) and extending over the pixelated element (12) and a part of the first metal layer (16), the first metal layer (16) and the second metal layer (20) forming an air-filled light path (38) to the pixelated element (12). The air-filled light path (38) is formed by creation of holes in the first dielectric layer (14) and the second dielectric layer (18), filling the holes with sacrificial materials, and removal of the sacrificial materials after deposition and patterning of the second metal layer (20). This yields an IC having a low-loss light path to the pixelated element (12). The light path may act as a color filter, e.g. a Fabry-Perot color filter.
摘要翻译：本发明涉及一种集成电路（IC）的制造方法，该集成电路（IC）包括基板（10），该基板（10）包括像素化元件（12）和到像素化元件（12）的光路（38）。所述IC包括覆盖所述衬底（10）而不是所述像素化元件（12）的第一介电层（14），覆盖所述第一介电层（14）的一部分的第一金属层（16），第二介电层（18））覆盖第一介电层（14）的另一部分，覆盖第二介电层（18）的一部分并在像素化元件（12）上延伸的第二金属层（20）和第一金属层（16）的一部分），第一金属层（16）和第二金属层（20）形成到像素化元件（12）的充气光路（38）。充气光路（38）通过在第一电介质层（14）和第二电介质层（18）中产生孔而形成，用牺牲材料填充孔，并且在沉积和图案化之后去除牺牲材料第二金属层（20）。这产生具有到像素化元件（12）的低损耗光路的IC。光路可以用作滤色器，例如，法布里 - 珀罗滤镜。

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