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1. 发明申请

WO2011030842A1 DEAD-TIME GENERATING CIRCUIT AND MOTOR CONTROL APPARATUS 审中-公开
标题翻译：死机发电电路和电机控制装置
公开(公告)号：WO2011030842A1
公开(公告)日：2011-03-17
申请号：PCT/JP2010/065570
申请日：2010-09-03
申请人： RICOH COMPANY, LTD. , UEDA, Yasuo , TOKUDA, Masashi , TSUKAGOSHI, Toshihiro
发明人： UEDA, Yasuo , TOKUDA, Masashi , TSUKAGOSHI, Toshihiro
IPC分类号： H02M7/537
CPC分类号： H02M1/38 , H03K5/1515 , H03K17/16
摘要： A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.
摘要翻译：死时间发生电路包括恒流电路; 产生电容器充电电流的电流产生电路; 以及接收死区时间控制信号和比较器信号的控制电路。控制电路基于死区时间控制信号和比较器信号产生死区时间产生信号，并且基于死区时间产生信号产生充电/放电信号。电容器的充电或放电根据充电/放电信号由电容器充电电流控制。将电容器的电压与阈值电压进行比较，以便当电容器的电压超过阈值电压时产生比较器信号。控制电路在从死区时间控制信号的上升或下降定时经过延迟时间直到控制电路接收到比较器信号为止的时间开始产生充电/放电信号。

2. 发明公开

EP1953918A1 PLL CONTROL CIRCUIT 审中-公开
标题翻译： PLL-STEUERSCHALTUNG
公开(公告)号：EP1953918A1
公开(公告)日：2008-08-06
申请号：EP06823216.4
申请日：2006-11-01
申请人： NEC Corporation , Ricoh Company, Ltd.
发明人： OOTSUKI, Michihito , SUKEKAWA, Masazumi , IWASAKI, Mitsutaka , TSUKAGOSHI, Toshihiro
IPC分类号： H03L7/14
CPC分类号： H03L7/183 , H03L7/14
摘要： A PLL control circuit, which outputs a PLL clock in response to a reference clock, is provided with a frequency adjustment circuit which performs frequency adjustment such that the PLL clock frequency is substantially constant even when the reference clock varies. The frequency adjustment circuit changes a set value in a counter, which determines the PLL clock frequency, in accordance with the variation in the reference clock frequency.
摘要翻译： PLL控制电路响应于参考时钟输出PLL时钟，该频率调节电路执行频率调整，使得即使参考时钟变化，PLL时钟频率也基本恒定。频率调整电路根据参考时钟频率的变化改变计数器中的设定值，该设定值决定了PLL时钟频率。

3. 发明授权

EP2476195B8 DEAD-TIME GENERATING CIRCUIT AND MOTOR CONTROL APPARATUS 有权
标题翻译：死时间发生电路和电机控制装置
公开(公告)号：EP2476195B8
公开(公告)日：2018-03-28
申请号：EP10815437.8
申请日：2010-09-03
申请人： Ricoh Company, Ltd.
发明人： UEDA, Yasuo , TOKUDA, Masashi , TSUKAGOSHI, Toshihiro
IPC分类号： H02M1/38 , H03K5/151 , H03K17/16 , H02M7/537
CPC分类号： H02M1/38 , H03K5/1515 , H03K17/16
摘要： A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.

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