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1. 发明申请

WO2014051545A1 DIGITALLY PHASE LOCKED LOW DROPOUT REGULATOR 审中-公开
标题翻译：数字相位锁定低压差型稳压器
公开(公告)号：WO2014051545A1
公开(公告)日：2014-04-03
申请号：PCT/US2012/057066
申请日：2012-09-25
申请人： RAYCHOWDHURY, Arijit , SOMASEKHAR, Dinesh , TSCHANZ, James W. , DE, Vivek K.
发明人： RAYCHOWDHURY, Arijit , SOMASEKHAR, Dinesh , TSCHANZ, James W. , DE, Vivek K.
IPC分类号： G05F1/10 , G05F1/40
CPC分类号： G05F1/577 , G05F1/468 , G05F1/56 , G06F1/06 , G06F1/26 , H03L7/085 , Y10T307/406
摘要： Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.
摘要翻译：描述了一种装置，包括：第一振荡器，用于产生第一时钟信号第二振荡器以产生第二时钟信号; 相位频率检测器，用于检测第一和第二时钟信号之间的相位差，并产生相位差; 以及耦合到负载的输出级，以根据相位差产生用于负载的电源。

2. 发明申请

WO2013002868A2 CIRCUITS AND METHODS FOR MEMORY 审中-公开
标题翻译：记忆的电路和方法
公开(公告)号：WO2013002868A2
公开(公告)日：2013-01-03
申请号：PCT/US2012/032688
申请日：2012-04-09
申请人： INTEL CORPORATION , KULKARNI, Jaydeep P. , SOMASEKHAR, Dinesh , TSCHANZ, James W. , DE, Vivek K.
发明人： KULKARNI, Jaydeep P. , SOMASEKHAR, Dinesh , TSCHANZ, James W. , DE, Vivek K.
CPC分类号： G11C7/02 , G11C11/419
摘要： Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented.
摘要翻译：给出了可以允许较小的最小信元供应（Vmin）而不必增加设备尺寸的数据依赖提升（DDB）位单元的实施例。

3. 发明申请

WO2013089698A1 MULTI-SUPPLY SEQUENTIAL LOGIC UNIT 审中-公开
标题翻译：多供应序列逻辑单元
公开(公告)号：WO2013089698A1
公开(公告)日：2013-06-20
申请号：PCT/US2011/064848
申请日：2011-12-14
申请人： INTEL CORPORATION , RAYCHOWDHURY, Arijit , KULKARNI, Jaydeep , TSCHANZ, James W.
发明人： RAYCHOWDHURY, Arijit , KULKARNI, Jaydeep , TSCHANZ, James W.
IPC分类号： G06F1/04 , G06F1/26
CPC分类号： H03K19/017509 , G06F1/10 , G06F1/3296 , Y02D10/172
摘要： Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.
摘要翻译：这里描述了用于减少处理器中的顺序逻辑单元的时钟到输出延迟的装置，方法和系统。所述装置包括顺序单元，包括：数据路径，用于接收包括在第一电源电平上操作的逻辑门的输入信号，所述数据路径以产生输出信号; 以及时钟路径，包括用于在第二电源电平上操作的逻辑门，所述时钟路径的逻辑门使用采样信号对所述输入信号进行采样以产生所述输出信号，其中所述第二电源电平高于所述第一电力供应水平。该装置改善（即减少）顺序单元的建立时间，并允许处理器以最小工作电压（Vmin）运行，而不降低顺序单元的性能。

4. 发明申请

WO2013085499A1 LOW POWER VOICE DETECTION 审中-公开
标题翻译：低功率语音检测
公开(公告)号：WO2013085499A1
公开(公告)日：2013-06-13
申请号：PCT/US2011/063622
申请日：2011-12-06
申请人： INTEL CORPORATION , RAYCHOWDHURY, Arijit , BELTMAN, Willem M. , TSCHANZ, James W. , TOKUNAGA, Carlos , DEISHER, Michael E. , WALSH, Thomas E.
发明人： RAYCHOWDHURY, Arijit , BELTMAN, Willem M. , TSCHANZ, James W. , TOKUNAGA, Carlos , DEISHER, Michael E. , WALSH, Thomas E.
IPC分类号： G10L19/00 , G10L11/00
CPC分类号： G10L15/20 , G06F1/3234 , G06F17/142 , G10L15/22 , G10L15/285 , G10L21/0208 , G10L21/0232 , G10L25/18 , G10L25/84 , G10L2015/223 , G10L2021/02087
摘要： Methods of enabling voice processing with minimal power consumption includes recording time-domain audio signal at a first clock frequency and a first voltage, and performing Fast Fourier Transform (FFT) operations on the time-domain audio signal at a second clock frequency to generate frequency-domain audio signal. The frequency domain audio signal may be enhanced to obtain better signal to noise ratio, through one or multiple filtering and enhancing techniques. The enhanced audio signal may be used to generate the total signal energy and estimate the background noise energy. Decision logic may determine from the signal energy and the background noise, the presence or absence of the human voice. The first clock frequency may be different from the second clock frequency.
摘要翻译：以最小功耗实现语音处理的方法包括以第一时钟频率和第一电压记录时域音频信号，并且以第二时钟频率对时域音频信号执行快速傅立叶变换（FFT）操作以产生频率域音频信号。可以通过一个或多个滤波和增强技术来增强频域音频信号以获得更好的信噪比。增强音频信号可用于产生总信号能量并估计背景噪声能量。决策逻辑可以根据信号能量和背景噪声来确定人类语音的存在或不存在。第一时钟频率可以不同于第二时钟频率。

5. 发明申请

WO2013100983A1 RESILIENT REGISTER FILE CIRCUIT FOR DYNAMIC VARIATION TOLERANCE AND METHOD OF OPERATING THE SAME 审中-公开
标题翻译：用于动态变化公差的弹性寄存器文件电路及其操作方法
公开(公告)号：WO2013100983A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067632
申请日：2011-12-28
申请人： INTEL CORPORATION , KULKARNI, Jaydeep P. , BOWMAN, Keith A. , TSCHANZ, James W. , DE, Vivek K.
发明人： KULKARNI, Jaydeep P. , BOWMAN, Keith A. , TSCHANZ, James W. , DE, Vivek K.
IPC分类号： G11C29/42
CPC分类号： G06F11/1068 , G06F9/30141 , G06F9/3861 , G06F11/0751 , G06F11/1008 , G11C7/18 , G11C29/42 , G11C29/52
摘要： The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
摘要翻译：所公开的系统和方法检测并校正由于减少或消除CPU的电源电压保护带和/或频率保护带而可能发生的寄存器文件读取路径错误，从而提高了系统的总体能量效率。

6. 发明申请

WO2015023290A1 MEMORY CELL WITH RETENTION USING RESISTIVE MEMORY 审中-公开
标题翻译：使用电阻记忆的记忆单元
公开(公告)号：WO2015023290A1
公开(公告)日：2015-02-19
申请号：PCT/US2013/055332
申请日：2013-08-16
申请人： AUGUSTINE, Charles , TOKUNAGA, Carlos , TSCHANZ, James W. , INTEL CORPORATION
发明人： AUGUSTINE, Charles , TOKUNAGA, Carlos , TSCHANZ, James W.
IPC分类号： G11C11/41 , H04L25/18
CPC分类号： G11C14/0081 , G11C11/1697 , G11C13/0011 , G11C14/0072 , G11C14/009
摘要： Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: a memory element including cross-coupled cells having a first node and a second node; a first transistor coupled to the first node; a second transistor coupled to the second node; and a resistive memory element coupled to the first and second transistors.
摘要翻译：描述了一种包括使用电阻性存储器保持的存储单元的装置。该装置包括：存储元件，其包括具有第一节点和第二节点的交叉耦合小区; 耦合到所述第一节点的第一晶体管; 耦合到所述第二节点的第二晶体管; 以及耦合到第一和第二晶体管的电阻性存储元件。

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