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1. 发明申请

WO2009086142A4 ASYMMETRIC COMMUNICATION ON SHARED LINKS 审中-公开
标题翻译：共享链路上的不对称通信
公开(公告)号：WO2009086142A4
公开(公告)日：2009-10-15
申请号：PCT/US2008087743
申请日：2008-12-19
申请人： RAMBUS INC , OH KYUNG SUK , WILSON JOHN , WARE FREDERICK , KIM WOOPOUNG , KIZER JADE M , LEIBOWITZ BRIAN S , LUO LEI , EBLE JOHN CRONAN
发明人： OH KYUNG SUK , WILSON JOHN , WARE FREDERICK , KIM WOOPOUNG , KIZER JADE M , LEIBOWITZ BRIAN S , LUO LEI , EBLE JOHN CRONAN
IPC分类号： G06F13/42 , H04L25/49
CPC分类号： G06F13/4243 , H04L25/4906 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.
摘要翻译：描述了经由共享链路在两个设备之间传送双向数据的系统的实施例。在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。数据可以在传输之前被编码为一系列并行码字。每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

2. 发明申请

WO2009086078A4 RECEIVER FOR MULTI-WIRE COMMUNICATION WITH REDUCED INPUT CAPACITANCE 审中-公开
标题翻译：具有降低输入电容的多线通信接收器
公开(公告)号：WO2009086078A4
公开(公告)日：2009-11-05
申请号：PCT/US2008087639
申请日：2008-12-19
申请人： RAMBUS INC , WARE FREDERICK , WILSON JOHN , OH KYUNG SUK , LEIBOWITZ BRIAN S , KIZER JADE M , LUO LEI
发明人： WARE FREDERICK , WILSON JOHN , OH KYUNG SUK , LEIBOWITZ BRIAN S , KIZER JADE M , LUO LEI
IPC分类号： G06F13/42 , H04L25/49
CPC分类号： G06F13/4243 , H04L25/4906 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a device that receives and decodes a series of parallel symbol sets over a series of time intervals is described. In this device, symbols in a respective parallel symbol set are received on nodes. Each node receives a respective symbol, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). Differential amplifiers in the device provide primary comparison results, each of which compares symbols received on pairs of the links, and generation circuits in the device provide secondary comparison results from the primary comparison results. A decoder in the device decodes a respective parallel symbol set from the primary and secondary comparison results to recover encoded data.
摘要翻译：描述了通过一系列时间间隔接收和解码一系列并行符号集的设备的实施例。在该装置中，各个并行符号组中的符号在节点上被接收。每个节点接收相应的符号，其可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）。器件中的差分放大器提供初步比较结果，每个比较结果比较了在链路对上接收到的符号，并且器件中的发生电路提供了主要比较结果的二次比较结果。设备中的解码器从主要和次要比较结果解码相应的并行符号集合以恢复编码数据。

3. 发明申请

WO2004077524A3 METHOD AND APPARATUS FOR TEST AND CHARACTERIZATION OF SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：半导体元件测试和表征的方法和装置
公开(公告)号：WO2004077524A3
公开(公告)日：2005-10-27
申请号：PCT/US2004005620
申请日：2004-02-25
申请人： RAMBUS INC , WARE FREDERICK , BEST SCOTT , CHANG TIMOTHY , PEREGO RICHARD , TSERN ELY , MITCHELL JEFF
发明人： WARE FREDERICK , BEST SCOTT , CHANG TIMOTHY , PEREGO RICHARD , TSERN ELY , MITCHELL JEFF
IPC分类号： G01R31/317 , G06F11/24 , H01L21/44
CPC分类号： G11C29/56004 , G01R31/31707 , G06F11/24 , G11C2029/5602
摘要： A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.
摘要翻译：提供了用于测试和表征电路的方法和装置。在一个实施例中，半导体部件的高速接口包括高速测试电路。高速测试电路无需外部高速测试系统进行测试和表征。在一个实施例中，高速测试电路包括测试图形生成电路和各种差分比较器，用于在测试和表征期间将低带宽参考信号与接口信号进行比较。在一个实施例中，包括测试电路的接口可以测试自身或另一接口。在一个实施例中，定时参考信号使彼此测试的两个接口的各个参数解耦，以避免由诸如接收机参数和发射机参数的各个接口电路参数的组合引入的任何错误。测试可以在晶片级，元件级和系统中执行。

4. 发明申请

WO2009032928A8 METHOD AND APPARATUS TO REPAIR DEFECTS IN NONVOLATILE SEMICONDUCTOR MEMORY DEVICES 审中-公开
标题翻译：在非易失性半导体存储器件中修复缺陷的方法和装置
公开(公告)号：WO2009032928A8
公开(公告)日：2010-04-15
申请号：PCT/US2008075261
申请日：2008-09-04
申请人： RAMBUS INC , BRONNER GARY B , LI MING , MULLEN DONALD R , WARE FREDERICK , DONNELLY KEVIN S
发明人： BRONNER GARY B , LI MING , MULLEN DONALD R , WARE FREDERICK , DONNELLY KEVIN S
IPC分类号： G11C16/34
CPC分类号： G11C16/349 , G11C16/3418 , H01L23/3128 , H01L23/345 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2924/15311 , H01L2924/19107 , H01L2924/00012 , H01L2924/00
摘要： A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed.
摘要翻译：一种修复非易失性半导体存储器件以消除缺陷的方法包括监测包含在半导体封装中的非易失性半导体存储器件的存储器耐久性指示器。确定记忆耐力指示符是否超过预定义的限制。最后，响应于确定存储器耐力指示符超出预定义的限制，器件被退火。

5. 发明申请

WO2009032928A2 METHOD AND APPARATUS TO REPAIR DEFECTS IN NONVOLATILE SEMICONDUCTOR MEMORY DEVICES 审中-公开
标题翻译：修复非易失性半导体存储器件缺陷的方法和装置
公开(公告)号：WO2009032928A2
公开(公告)日：2009-03-12
申请号：PCT/US2008075261
申请日：2008-09-04
申请人： RAMBUS INC , BRONNER GARY B , LI MING , MULLEN DONALD R , WARE FREDERICK , DONNELLY KEVIN S
发明人： BRONNER GARY B , LI MING , MULLEN DONALD R , WARE FREDERICK , DONNELLY KEVIN S
IPC分类号： G11C16/34
CPC分类号： G11C16/349 , G11C16/3418 , H01L23/3128 , H01L23/345 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2924/15311 , H01L2924/19107 , H01L2924/00012 , H01L2924/00
摘要： A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed.
摘要翻译：一种修复非易失性半导体存储器件以消除缺陷的方法包括监测包含在半导体封装中的非易失性半导体存储器件的存储器耐久指示器。确定内存耐久性指标是否超过预定义的限制。最后，响应于确定存储器耐久性指标超过预定限制，对设备进行退火。

6. 发明申请

WO2009099788A4 MULTI-DROP SIGNALING SYSTEM AND METHOD EMPLOYING SOURCE-TERMINATION 审中-公开
标题翻译：多滴信号系统和采用源端的方法
公开(公告)号：WO2009099788A4
公开(公告)日：2009-11-19
申请号：PCT/US2009031985
申请日：2009-01-26
申请人： RAMBUS INC , WARE FREDERICK , STOTT BRET G
发明人： WARE FREDERICK , STOTT BRET G
IPC分类号： G06F13/42
CPC分类号： G06F13/4239 , G06F13/1689 , Y02D10/14 , Y02D10/151
摘要： A signaling system employs parallel termination for a timing reference signal and series termination for information signals that may be sampled using the timing reference signal. In this way, the system may provide desired levels of signal performance and power consumption. In addition, the system may be configured such that the initial wavefronts of these signals may travel in opposite directions along complementary signaling paths. For example, a timing reference signal that travels from a driving device (e.g., a memory controller) to several destination devices (e.g., memory devices) in a multi-drop/fly-by fashion may arrive at the destination devices in a given order. In contrast, associated information signals may travel from the driving device to the destination devices such that they arrive at the destination devices in the opposite order.
摘要翻译：信令系统对于定时参考信号采用并行端接，对于可以使用定时参考信号采样的信息信号采用串联端接。这样，该系统可以提供期望水平的信号性能和功耗。另外，系统可以被配置为使得这些信号的初始波前可以沿着互补的信令路径沿着相反的方向行进。例如，以多点/飞行方式从驱动装置（例如，存储器控制器）行进到若干目的地装置（例如，存储器装置）的定时参考信号可以以给定顺序到达目的地装置。相反，相关联的信息信号可以从驱动设备行进到目的地设备，使得它们以相反的顺序到达目的地设备。

7. 发明申请

WO2009099788A3 MULTI-DROP SIGNALING SYSTEM AND METHOD EMPLOYING SOURCE-TERMINATION 审中-公开
公开(公告)号：WO2009099788A3
公开(公告)日：2009-10-01
申请号：PCT/US2009031985
申请日：2009-01-26
申请人： RAMBUS INC , WARE FREDERICK , STOTT BRET G
发明人： WARE FREDERICK , STOTT BRET G
IPC分类号： G06F13/42
CPC分类号： G06F13/4239 , G06F13/1689 , Y02D10/14 , Y02D10/151
摘要： A signaling system employs parallel termination for a timing reference signal and series termination for information signals that may be sampled using the timing reference signal. In this way, the system may provide desired levels of signal performance and power consumption. In addition, the system may be configured such that the initial wavefronts of these signals may travel in opposite directions along complementary signaling paths. For example, a timing reference signal that travels from a driving device (e.g., a memory controller) to several destination devices (e.g., memory devices) in a multi-drop/fly-by fashion may arrive at the destination devices in a given order. In contrast, associated information signals may travel from the driving device to the destination devices such that they arrive at the destination devices in the opposite order.

8. 发明申请

WO2009055103A4 LOW-POWER SOURCE-SYNCHRONOUS SIGNALING 审中-公开
标题翻译：低功耗源同步信号
公开(公告)号：WO2009055103A4
公开(公告)日：2009-08-06
申请号：PCT/US2008069250
申请日：2008-07-03
申请人： RAMBUS INC , ZERBE JARED L , WARE FREDERICK
发明人： ZERBE JARED L , WARE FREDERICK
IPC分类号： G06F13/42
CPC分类号： G11C11/4076 , G06F1/04 , G06F13/4243 , G11C7/04 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , H04L7/0008 , Y02B60/1228 , Y02B60/1235 , Y02D10/14 , Y02D10/151
摘要： Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.
摘要翻译：在集成电路装置的系统内，第一和第二信号从第一集成电路装置间歇地传输到第二集成电路装置。第二集成电路器件基于第二信号的转变生成定时信号，并且响应于定时信号的转变生成第一信号的采样。第二集成电路器件还基于第一信号的采样产生定时误差信息，该定时误差信息使得能够调节定时信号和第一信号的相对相位。

9. 发明申请

WO2009055103A2 LOW-POWER SOURCE-SYNCHRONOUS SIGNALING 审中-公开
公开(公告)号：WO2009055103A2
公开(公告)日：2009-04-30
申请号：PCT/US2008069250
申请日：2008-07-03
申请人： RAMBUS INC , ZERBE JARED L , WARE FREDERICK
发明人： ZERBE JARED L , WARE FREDERICK
IPC分类号： G06F13/42
CPC分类号： G11C11/4076 , G06F1/04 , G06F13/4243 , G11C7/04 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , H04L7/0008 , Y02B60/1228 , Y02B60/1235 , Y02D10/14 , Y02D10/151
摘要： Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.

10. 发明专利

AT448548T 未知
公开(公告)号：AT448548T
公开(公告)日：2009-11-15
申请号：AT05799571
申请日：2005-09-12
申请人： RAMBUS INC
发明人： WARE FREDERICK , LAI LAWRENCE , BELLOWS CHAD , RICHARDSON WAYNE S
IPC分类号： G11C8/12 , G11C8/16

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