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1. 发明申请

WO2012145117A3 MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES 审中-公开
标题翻译：存储器组件和控制器，用于校准多个同步时序参考
公开(公告)号：WO2012145117A3
公开(公告)日：2013-01-17
申请号：PCT/US2012029893
申请日：2012-03-21
申请人： RAMBUS INC , GIOVANNINI THOMAS J , BEST SCOTT C , LUO LEI , SHAEFFER IAN
发明人： GIOVANNINI THOMAS J , BEST SCOTT C , LUO LEI , SHAEFFER IAN
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/227 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C29/56
摘要： A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.
摘要翻译：第一定时参考信号和第二定时参考信号被发送到存储器件。第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。从存储装置接收多个串行数据模式。第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。时间指示器均使用单个采样器进行测量。基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

2. 发明申请

WO2011106055A4 COORDINATING MEMORY OPERATIONS USING MEMORY-DEVICE GENERATED REFERENCE SIGNALS 审中-公开
标题翻译：使用存储器设备生成的参考信号协调存储器操作
公开(公告)号：WO2011106055A4
公开(公告)日：2011-11-03
申请号：PCT/US2010058542
申请日：2010-12-01
申请人： RAMBUS INC , BEST SCOTT C , SHAEFFER IAN
发明人： BEST SCOTT C , SHAEFFER IAN
IPC分类号： G06F13/16 , G06F13/38
CPC分类号： G06F13/1689 , G06F3/061 , G06F3/0659 , G06F3/0683 , G11C11/4076 , G11C11/409 , G11C11/4093 , Y02B60/1228 , Y02D10/14
摘要： A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.
摘要翻译：存储器系统包括耦合到多个存储器设备的存储器控制器。每个存储器设备包括振荡器，该振荡器生成内部参考信号，该内部参考信号以作为存储器设备内的物理设备结构的函数的频率振荡。内部参考信号的频率因此是设备特定的。每个存储器设备从其内部参考信号产生共享参考信号并将共享参考信号传送到公共存储器控制器。存储器控制器使用共享参考信号从每个存储器设备恢复设备特定的频率信息，然后以与相应的内部参考信号兼容的频率与每个存储器设备通信。

3. 发明申请

WO2011081691A3 EXPANDABLE ASYMMETRIC-CHANNEL MEMORY SYSTEM 审中-公开
标题翻译：可扩展的不对称通道存储系统
公开(公告)号：WO2011081691A3
公开(公告)日：2011-10-06
申请号：PCT/US2010051318
申请日：2010-10-04
申请人： RAMBUS INC , SHAEFFER IAN , VAIDYANATH ARUN , MUKHERJEE SANKU
发明人： SHAEFFER IAN , VAIDYANATH ARUN , MUKHERJEE SANKU
IPC分类号： G06F13/14 , G06F13/16 , G06F13/38
CPC分类号： G06F13/1668 , G06F1/3275 , G06F12/0246 , G06F13/1678 , G06F13/1684 , G06F13/4022 , G06F13/4068 , G06F13/4072 , Y02B60/1228 , Y02B60/1235 , Y02D10/14 , Y02D10/151
摘要： An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.
摘要翻译：一种可扩展存储器系统，其使固定信令带宽能够在专用存储器通道之间可配置地重新分配。具有逐渐减小的宽度的存储器通道专用于相应的存储器插槽，从而使得能够相对于每个存储器插座的点对点信令，而不会对每个插座的全宽度存储器通道的无负载的插座进行信号损害遍历或昂贵的复制。

4. 发明申请

WO2007136655A2 SYSTEM TO DETECT AND IDENTIFY ERRORS IN CONTROL INFORMATION, READ DATA AND/OR WRITE DATA 审中-公开
标题翻译：在控制信息中检测和识别错误的系统，读取数据和/或写入数据
公开(公告)号：WO2007136655A2
公开(公告)日：2007-11-29
申请号：PCT/US2007011733
申请日：2007-05-16
申请人： RAMBUS INC , SHAEFFER IAN , HAMPEL CRAIG
发明人： SHAEFFER IAN , HAMPEL CRAIG
CPC分类号： G06F11/1004
摘要： An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction. The CRC code generated by the integrated circuit then may be compared to a CRC code generated by the controller device to determine whether an error occurred. The controller device generates and stores a plurality of CRC codes, corresponding to control information, write data and read data. The controller device then compares the CRC codes generated by the controller device with CRC codes generated and stored in the integrated circuit to determine whether an error has occurred during a particular transaction.
摘要翻译：集成电路，例如集成电路存储器或缓冲器件，方法和系统以及其他实施例中，分别生成对应于控制信息，写入数据和读取数据事务的多个错误代码，例如CRC代码。多个单独产生的CRC码被记录或存储在相应的存储电路中，例如循环缓冲器。对应于每个事务的存储的多个CRC码可以用于确定在特定事务期间是否发生错误，并且因此是否发出特定事务的重试。集成电路包括比较电路，用于将由集成电路产生的CRC码与由控制器装置提供的CRC码进行比较。使用在读取事务期间未被使用的数据掩码信号线将对应于读取数据的CRC码传送到控制器设备。然后可以将由集成电路生成的CRC码与由控制器设备生成的CRC码进行比较，以确定是否发生错误。控制器装置产生并存储对应于控制信息，写数据和读数据的多个CRC码。然后，控制器设备将由控制器设备产生的CRC码与生成并存储在集成电路中的CRC码进行比较，以确定在特定交易期间是否发生错误。

5. 发明申请

WO2012021379A3 VERIFY BEFORE PROGRAM RESUME FOR MEMORY DEVICES 审中-公开
标题翻译：验证存储设备的程序恢复之前进行验证
公开(公告)号：WO2012021379A3
公开(公告)日：2012-04-05
申请号：PCT/US2011046664
申请日：2011-08-04
申请人： RAMBUS INC , SHAEFFER IAN , HAUKNESS BRENT S
发明人： SHAEFFER IAN , HAUKNESS BRENT S
IPC分类号： G11C16/34 , G11C7/10 , G11C16/10
CPC分类号： G06F12/00 , G11C16/10 , G11C16/344
摘要： A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.
摘要翻译：公开了一种将数据编程到包括存储器单元阵列的存储器装置中的方法。该方法包括接收寻址用于编程操作的若干存储器单元的至少一个编程命令以编程存储器单元中的数据。通过迭代地执行至少一个编程/验证周期来执行至少一个编程命令，以用编程数据对编址的存储单元进行增量编程。辅助命令可以在启动之后但是在完成编程操作之前被选择性地接收。编程操作可以通过首先验证存储器单元，然后执行至少一个编程/验证周期来选择性地恢复。

6. 发明申请

WO2012064638A3 MEMORY ACCESS DURING MEMORY CALIBRATION 审中-公开
标题翻译：存储器校准期间的存储器访问
公开(公告)号：WO2012064638A3
公开(公告)日：2012-08-16
申请号：PCT/US2011059550
申请日：2011-11-07
申请人： RAMBUS INC , SHAEFFER IAN , WARE FREDERICK A
发明人： SHAEFFER IAN , WARE FREDERICK A
IPC分类号： G06F13/14 , G06F12/00 , G06F13/38
CPC分类号： G06F12/1458 , G06F12/023 , G06F13/16 , G06F13/1657 , G06F13/1684 , G06F13/1694 , G06F2212/1044 , G06F2212/1052
摘要： A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.
摘要翻译：一种多列存储器系统，其中在存储器控制器和一列存储器之间执行校准操作，同时在控制器和其他存储器列之间传输数据。存储器控制器执行校准操作，该校准操作校准与存储器控制器和第一存储器中的存储器设备之间的第一数据总线有关的数据传输有关的参数。当控制器执行校准操作时，控制器还通过第二数据总线与第二存储器中的存储器设备传送数据。

7. 发明申请

WO2012122381A3 POWER-MANAGEMENT FOR INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路的电源管理
公开(公告)号：WO2012122381A3
公开(公告)日：2012-12-27
申请号：PCT/US2012028289
申请日：2012-03-08
申请人： RAMBUS INC , SHAEFFER IAN , LEI LUO , GOPALAKRISHAN LIJI
发明人： SHAEFFER IAN , LEI LUO , GOPALAKRISHAN LIJI
IPC分类号： G11C7/22 , G06F1/32 , G11C7/10
CPC分类号： G11C11/4076 , G06F1/04 , G06F1/08 , G06F1/3234 , G06F1/3237 , G11C7/1072 , G11C7/20 , G11C7/22 , G11C11/4072 , G11C11/4074 , G11C11/4087 , G11C11/4096 , Y02D10/128 , Y02D50/20
摘要： An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
摘要翻译：集成电路包括具有控制定时域和数据定时域的物理层接口以及响应于第一事件而在功率节省模式改变期间启用控制定时域的电路，并且响应于数据定时域启用数据定时域到第二个事件。控制时序域可以包括耦合到命令和地址路径的接口电路，并且数据时序域可以包括耦合到数据路径的接口电路。

8. 发明申请

WO2012109185A2 OFFSETTING CLOCK PACKAGE PINS IN A CLAMSHELL TOPOLOGY TO IMPROVE SIGNAL INTEGRITY 审中-公开
标题翻译：在CLAMSHELL拓扑中优化时钟包，以提高信号的完整性
公开(公告)号：WO2012109185A2
公开(公告)日：2012-08-16
申请号：PCT/US2012024066
申请日：2012-02-07
申请人： RAMBUS INC , SHAEFFER IAN , KOLLIPARA RAVINDRANATH
发明人： SHAEFFER IAN , KOLLIPARA RAVINDRANATH
IPC分类号： G11C5/02 , G11C7/10
CPC分类号： G11C5/02 , G11C5/04 , G11C5/06 , H01L23/3128 , H01L23/48 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2924/00013 , H05K1/181 , H05K2201/10159 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： The disclosed embodiments relate to the design of a memory system which includes a set of one or more memory modules, wherein each memory module in the set has a clamshell configuration, wherein pairs of opposing memory packages containing memory chips are located on opposite sides of the memory module. The memory system also includes a multi-drop path containing signal lines which pass through the set of memory modules, and are coupled to memory packages in the set of memory modules. For a given signal line in the multi-drop path, a first memory package and a second memory package that comprise a given pair of opposing memory packages are coupled to the given signal line at a first location and a second location, respectively, wherein the first location and the second location are separated from each other by a distance d1 along the given signal line.
摘要翻译：所公开的实施例涉及包括一组一个或多个存储器模块的存储器系统的设计，其中该组中的每个存储器模块具有蛤壳式配置，其中包含存储器芯片的对相对存储器组的对位于内存模块存储器系统还包括一个包含通过该组存储器模块的信号线的多点路径，并且耦合到该组存储器模块中的存储器封装。对于多分支路径中的给定信号线，包括给定的一对相对的存储器封装的第一存储器封装和第二存储器封装分别在第一位置和第二位置耦合到给定的信号线，其中，第一位置和第二位置沿着给定信号线彼此分开一段距离d1。

9. 发明专利

GB2474592A Fractional program commands for memory devices 未知
公开(公告)号：GB2474592A
公开(公告)日：2011-04-20
申请号：GB201019496
申请日：2009-05-06
申请人： RAMBUS INC
发明人： HAWKNESS BRENT S , SHAEFFER IAN , BRONNER GARY
IPC分类号： G11C16/10
摘要： A memory system (100B) includes an array of non-volatile memory cells (140) and a memory controller (110) having a first port (port connected to line 101) to receive a program command that addresses a number of the memory cells for a programming operation, having a second port (port connected to lines 102 and 103) coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

10. 发明专利

GB2474592B Fractional program commands for memory devices 未知
公开(公告)号：GB2474592B
公开(公告)日：2013-01-23
申请号：GB201019496
申请日：2009-05-06
申请人： RAMBUS INC
发明人： HAWKNESS BRENT S , SHAEFFER IAN , BRONNER GARY
IPC分类号： G11C16/10
摘要： A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

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