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    • 1. 发明专利
      JP2006060842A Delay-locked loop 有权
    • Delay-locked loop
    • 延迟锁定
    • JP2006060842A
    • 2006-03-02
    • JP2005253696
    • 2005-09-01
    • Rambus Inc , ラムバス・インコーポレーテッド
    • LEE THOMAS H , DONNELLY KEVIN S , HO TSYR-CHYANG , JOHNSON MARK G
    • G01R31/28 , H03L7/081 , H03L7/00 , H03L7/08 , H03L7/093 , H04L7/033
    • H03L7/0812
    • PROBLEM TO BE SOLVED: To provide a delay locked loop in which a voltage controlled oscillator (VCO) is obviated, power supply induction jitter is speedily obtained and suppressed to a minimum and a phase shift range is not limited. SOLUTION: The output of a phase comparator drives a differential charge pump which functions to integrate a phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Because the DLL adjusts the phase shifter until the output of the phase detector is high 50% of the time, on average, the relationship of the DLL output clock to the input reference clock depends only on the type of phase detector used. Furthermore, the DLL is controlled to minimize dither jitter while minimizing acquisition time. In addition, duty cycle correcting amplifiers are employed to produce a DLL output clock that has a desired duty cycle, for example 50%. COPYRIGHT: (C)2006,JPO&NCIPI
    • 要解决的问题：为了提供消除压控振荡器（VCO）的延迟锁定环路，快速获得电源感应抖动并将其抑制到最小，相移范围不受限制。

      解决方案：相位比较器的输出驱动差分电荷泵，其功能是使相位比较器输出信号随时间积分。 电荷泵输出控制无限幅度的移相器，可调节DLL输出的相位，使相位比较器的输出平均高达50％的时间。 因为DLL调整移相器直到相位检测器的输出高达50％的时间，平均而言，DLL输出时钟与输入参考时钟的关系仅取决于所使用的相位检测器的类型。 此外，DLL被控制以最小化抖动抖动，同时最小化采集时间。 此外，采用占空比校正放大器来产生具有期望占空比的DLL输出时钟，例如50％。 版权所有（C）2006，JPO＆NCIPI

    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明专利
      AU1738995A A phase detector with minimized phase detection error 未知
    • A phase detector with minimized phase detection error
    • AU1738995A
    • 1995-08-29
    • AU1738995
    • 1995-02-01
    • RAMBUS INC
    • DONNELLY KEVIN S , LEE THOMAS H , HO TSYR-CHYANG
    • G01R25/00 , H03K5/26 , H03L7/085
    • A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal. The second circuit is cross-coupled to the first circuit such that an error current generated by the second circuit cancels that generated by the first circuit such that the phase detector detects the phase difference between the first and second signals with minimized phase detection error.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明专利
      AU1686795A Voltage controlled phase shifter with unlimited range 未知
    • Voltage controlled phase shifter with unlimited range
    • AU1686795A
    • 1995-08-29
    • AU1686795
    • 1995-01-16
    • RAMBUS INC
    • LEE THOMAS H , DONNELLY KEVIN S , HO TSYR-CHYANG
    • H03H11/20
    • A voltage-controlled phase shift apparatus having an unlimited range for producing an output signal that varies in phase from an input signal by a predetermined phase difference. The phase shift apparatus includes a first delay circuit coupled to receive the input signal, the first delay circuit for outputting a first intermediate signal that is alpha degrees out of phase with the input signal, a second intermediate signal that is beta degrees out of phase with the first intermediate signal, a third intermediate signal that is 180 degrees out of phase with the first intermediate signal, and a fourth intermediate signal that is 180 degrees out of phase with the second intermediate signal. The phase shift apparatus also includes a phase interpolator circuit coupled to receive a control voltage signal and the first, second, third and fourth intermediate signals, the phase interpolator for phase mixing a selected pair of the first, second, third and fourth intermediate signals in response to the control voltage signal, the phase interpolator for outputting the output signal. A phase selector circuit coupled to the phase interpolator circuit and coupled to receive a phase slope signal and the control voltage signal selects the selected pair in response to the phase slope signal and the control voltage signal such that the output signal varies in phase from the input signal by the predetermined phase difference.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明专利
      AU1841895A Delay-locked loop 未知
    • Delay-locked loop
    • AU1841895A
    • 1995-08-29
    • AU1841895
    • 1995-02-09
    • RAMBUS INC
    • LEE THOMAS H , DONNELLY KEVIN S , HO TSYR-CHYANG , JOHNSON MARK GRIFFIN
    • G01R31/28 , H03L7/00 , H03L7/08 , H03L7/081 , H03L7/093
    • A delay locked loop (DLL) is described in which a phase detector compares the phase of the output of the DLL with that of a reference input. The output of the phase comparator drives a differential charge pump which functions to integrate the phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Because the DLL adjusts the phase shifter until the output of the phase detector is high 50% of the time, on average, the relationship of the DLL output clock to the input reference clock depends only on the type of phase detector used. For example, when a data receiver is used as the phase detector in the DLL, the output of the DLL is a clock signal which can be used as a sampling clock for data receivers elsewhere in the system, and is timed to sample data at the optional instant independent of temperature, supply voltage and process variations. Alternatively, a quadrature phase detector may be employed to generate a clock signal that possesses a quadrature (90 DEG ) relationship with a reference clock signal input. This may be used, for example, to generate a transmit clock for a data transmission device. Furthermore, the DLL is controlled to minimize dither jitter while minimizing acquisition time. In addition, duty cycle correcting amplifiers are employed to produce a DLL output clock that has a desired duty cycle, for example 50%. Additionally, the inputs to the charge pump are reversed in alternate quadrants of the phase plane in order to enable unlimited phase shift with a finite control voltage range.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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