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1. 发明授权

US06278333B1 Phase lock loop with dual state charge pump and method of operating the same 有权
标题翻译：具有双态电荷泵的锁相环及其操作方法
公开(公告)号：US06278333B1
公开(公告)日：2001-08-21
申请号：US09514802
申请日：2000-02-29
申请人： Quang C. Le , Ronald H. Deck , Richard B. Meador , David H. Minasi
发明人： Quang C. Le , Ronald H. Deck , Richard B. Meador , David H. Minasi
IPC分类号： H03L708
CPC分类号： H03L7/107 , H03L7/0893 , H03L7/0898 , H03L7/1976
摘要： A phase lock loop (100) includes a dual-state charge pump (120) having a first current source (220), a second current source (230) coupled in series to the first current source, a third current source (240), a fourth current source (250) coupled in series to the third current source, and control circuitry (210) coupled to the first, second, third, and fourth current sources. The charge pump can be programmed to be in an adapt mode with large up and down currents or in a normal mode with small up and down currents. The duration of the adapt mode can be programmed by a timer. The phase lock loop has a wide loop bandwidth and a faster lock time during the adapt mode and a narrow loop bandwidth and less phase noise during the normal mode.
摘要翻译：锁相环（100）包括具有第一电流源（220），与第一电流源串联耦合的第二电流源（230）的双态电荷泵（120），第三电流源（240）耦合到第三电流源的第四电流源（250）和耦合到第一，第二，第三和第四电流源的控制电路（210）。电荷泵可以编程为具有较大上下电流的适应模式，或者在正常模式下，具有较小的上下电流。适配模式的持续时间可以由定时器编程。在正常模式期间，锁相环具有较宽的环路带宽和适应模式下较快的锁定时间以及较窄的环路带宽和较小的相位噪声。

2. 发明授权

US06564039B1 Frequency generation circuit and method of operating a tranceiver 有权
标题翻译：频率发生电路及操作收发器的方法
公开(公告)号：US06564039B1
公开(公告)日：2003-05-13
申请号：US09515728
申请日：2000-02-29
申请人： Richard B. Meador , Ronald H. Deck , David J. Graham , David H. Minasi , Brian Shelton
发明人： Richard B. Meador , Ronald H. Deck , David J. Graham , David H. Minasi , Brian Shelton
IPC分类号： H04B140
CPC分类号： H04B1/406 , H03L7/23 , H04B2001/0491
摘要： A frequency generation circuit includes an oscillator (403), a comparator (413) coupled to the oscillator, a first divider (407) coupled to the comparator, a PLL (400) coupled to the first divider, a second divider (422) coupled to the PLL, a first multiplexor (409) coupled to the second divider, a third divider (408) coupled to the comparator and the first multiplexor, a second multiplexor (410) coupled to the comparator and the reference clock PLL, a fourth divider (411) coupled to the second multiplexor, a fifth divider (412) coupled to the comparator, and a seventh divider (450) coupled to the comparator. A method of operating a transceiver includes using the frequency generation circuit to provide a first clock signal, a second clock signal, a first reference frequency, and a second reference frequency for a first component, a second component, a third component, and a fourth component, respectively, of the transceiver.
摘要翻译：频率发生电路包括振荡器（403），耦合到振荡器的比较器（413），耦合到比较器的第一分频器（407），耦合到第一分频器的PLL（400），耦合到第一分频器耦合到所述PLL，耦合到所述第二分频器的第一多路复用器（409），耦合到所述比较器和所述第一多路复用器的第三分频器（408），耦合到所述比较器和所述参考时钟PLL的第二多路复用器（410）（411），耦合到所述第二多路复用器，耦合到所述比较器的第五分频器（412）和耦合到所述比较器的第七分频器（450）。操作收发器的方法包括使用频率产生电路为第一组件，第二组件，第三组件和第四组件提供第一时钟信号，第二时钟信号，第一参考频率和第二参考频率分别为收发器。

3. 发明授权

US06246213B1 Device having battery-save circuitry and method of operation 有权
标题翻译：具有电池保存电路和操作方法的装置
公开(公告)号：US06246213B1
公开(公告)日：2001-06-12
申请号：US09515247
申请日：2000-02-29
申请人： Richard B. Meador , Wayne W. Ballantyne , Ronald H. Deck , Habib Kilicaslan
发明人： Richard B. Meador , Wayne W. Ballantyne , Ronald H. Deck , Habib Kilicaslan
IPC分类号： H01M1044
CPC分类号： G06F1/324 , G06F1/24 , G06F1/3203 , G06F1/3287 , H01M10/44 , H02J9/005 , H04W52/029 , Y02D10/126 , Y02D10/171 , Y02D70/00
摘要： A device having battery-save circuitry includes a power-on reset circuit (603), an OR-gate (604) coupled to the power-on reset circuit (603), a current-boost timer circuit (602) coupled to the OR-gate (604), a reference oscillator (403) with a start-up current mode enabled by the current-boost timer circuit (602), and a low current secondary reference oscillator (613). A method of operating the device includes operating the device in a battery-save mode and an active mode. A first clock signal is used as a microprocessor clock signal while operating the device in the battery-save mode, and a second or third clock signal is used as the microprocessor clock signal while operating the device in the active mode.
摘要翻译：具有电池保存电路的装置包括上电复位电路（603），耦合到上电复位电路（603）的或门（604），耦合到OR的电流升压定时器电路（602） - 门（604），具有由电流升压定时器电路（602）使能的启动电流模式的参考振荡器（403）和低电流次参考振荡器（613）。操作该设备的方法包括以电池节省模式和活动模式操作该设备。第一时钟信号用作微处理器时钟信号，同时在电池保存模式下操作器件，并且在处于活动模式下操作器件时，使用第二或第三时钟信号作为微处理器时钟信号。

4. 发明授权

US06697016B1 Self adjustment of a frequency offset in a GPS receiver 有权
标题翻译：自动调整GPS接收机的频率偏移
公开(公告)号：US06697016B1
公开(公告)日：2004-02-24
申请号：US10260940
申请日：2002-09-30
申请人： Thomas E. Voor , Ronald H. Deck
发明人： Thomas E. Voor , Ronald H. Deck
IPC分类号： G01S502
CPC分类号： G01S19/235 , H03J2200/05
摘要： A global positioning system (GPS) receiver (102) has a reference oscillator (114) for use in synthesizing signals for use in receiving and acquiring GPS satellite signals by a GPS downconverter (110). Upon manufacture of the receiver (204), the receiver is tested and a factory frequency offset of the oscillator is determined (206). It has been found that the heat used in reflowing the solder used to attach receiver components causes the operating frequency of oscillator devices, such as crystals, to shift considerably. In addition, during a brief period after manufacture of the receiver, the frequency of the oscillator shifts back towards its original operating frequency, and so much so that the narrow search window used to search for a GPS carrier is inadequate, and it is likely that the receiver would not locate the desired carrier signal. The invention takes advantage of the time period after manufacture, when the frequency of the oscillator settles, and the first time unit is turned on, the receiver is used proactively with a wide search window (212) to determine an operating frequency offset. Then, for subsequent location determination operations, a narrow search window is used (222).
摘要翻译：全球定位系统（GPS）接收机（102）具有参考振荡器（114），用于合成用于由GPS下变频器（110）接收和获取GPS卫星信号的信号。在制造接收器（204）时，测试接收机并确定振荡器的出厂频率偏移（206）。已经发现，用于回流用于附接接收器部件的焊料的热量导致振荡器器件（例如晶体）的工作频率显着变化。另外，在制造接收机之后的短暂时间内，振荡器的频率向其原始工作频率转移，并且使得用于搜索GPS载波的窄搜索窗口不足，并且很可能接收机将不会定位所需的载波信号。本发明利用制造后的时间段，当振荡器的频率稳定并且第一时间单元被接通时，接收机主动地用广泛的搜索窗口（212）来使用以确定操作频率偏移。然后，对于随后的位置确定操作，使用窄搜索窗口（222）。

5. 发明授权

US06867734B2 System and method for frequency management in a communications positioning device 有权
标题翻译：通信定位装置中频率管理的系统和方法
公开(公告)号：US06867734B2
公开(公告)日：2005-03-15
申请号：US10439200
申请日：2003-05-15
申请人： Thomas E. Voor , Sameh W. Tawadrous , Ronald H. Deck
发明人： Thomas E. Voor , Sameh W. Tawadrous , Ronald H. Deck
IPC分类号： G01S19/12 , G01S1/00 , G01S19/23 , G01S19/25 , G01S19/35 , G01S19/48 , H03J7/06 , H04B1/16 , H04B1/38 , H04B1/40 , G01S5/14
CPC分类号： H03L7/23 , G01S19/235 , H03J7/065 , H03J2200/11 , H03L7/183 , H04B1/3805 , H04B1/403
摘要： A frequency management scheme for a hybrid communications/positioning device, such as a cellular/GPS or other combined device, generates a local clock signal for the communications portion of the device, using a crystal oscillator or other part. The oscillator output may be delivered to a phase locked loop to drive a high-frequency clock for the cellular or other communications portion of the hybrid device. A processor may determine frequency error between the phase locked loop and base station or other reference, to derive a digital frequency tracking message. A Doppler search or other logical control message may likewise be communicated from the processor to a GPS or other positioning receiver. The GPS receiver circuitry may consequently adjust Doppler center, window width or other parameters to enhance time to first fix or other performance. The architecture eliminates the need for a second crystal or other direct oscillator in the GPS receiver portion of the hybrid device, while still maintaining GPS performance. The architecture of the design also eliminates the need for frequency correcting elements in the crystal oscillator or other base reference oscillator or clock. The invention can furthermore be used in any system, radio, modem, transceiver, or receiver that has two or more receivers that share one reference or base oscillator or clock.
摘要翻译：用于诸如蜂窝/ GPS或其他组合设备的混合通信/定位设备的频率管理方案使用晶体振荡器或其他部分为设备的通信部分生成本地时钟信号。振荡器输出可以被传送到锁相环以驱动用于混合设备的蜂窝或其他通信部分的高频时钟。处理器可以确定锁相环和基站或其他参考之间的频率误差，以导出数字频率跟踪消息。多普勒搜索或其他逻辑控制消息同样可以从处理器传送到GPS或其他定位接收器。因此，GPS接收器电路可以调整多普勒中心，窗口宽度或其他参数，以增强第一次固定或其他性能的时间。该架构消除了在混合设备的GPS接收机部分中的第二晶体或其他直接振荡器的需要，同时仍然保持GPS性能。该设计的架构也消除了在晶体振荡器或其他基准参考振荡器或时钟中的频率校正元件的需要。本发明还可以用于具有共享一个参考或基本振荡器或时钟的两个或多个接收器的任何系统，无线电，调制解调器，收发器或接收器。

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