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1. 发明申请

WO2016209603A1 STRUCTURE AND METHOD FOR TUNABLE MEMORY CELLS INCLUDING FIN FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：包含Fin场效应晶体管的TUNABLE MEMORY CELL的结构和方法
公开(公告)号：WO2016209603A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/036084
申请日：2016-06-06
申请人： QUALCOMM INCORPORATED
发明人： YANG, Haining , LIU, Yanxiang
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L29/78 , H01L27/088 , H01L27/092 , H01L27/11 , H01L27/12
CPC分类号： H01L21/02 , G05B19/418 , G05B2219/45031 , H01L21/76895 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L27/0207 , H01L27/0886 , H01L27/0924 , H01L27/11 , H01L27/1104 , H01L27/1211 , H01L29/785
摘要： In a particular aspect, an integrated circuit includes a first gate structure coupled to a first fin field effect transistor (FinFET) device. The integrated circuit includes a second gate structure coupled to a second FinFET device. The first gate structure and the second gate structure are separated by a dielectric region. The integrated circuit further includes a metal contact having a first surface that is in contact with the dielectric region, the first gate structure, and the second gate structure.
摘要翻译：在特定方面，集成电路包括耦合到第一鳍式场效应晶体管（FinFET）器件的第一栅极结构。集成电路包括耦合到第二FinFET器件的第二栅极结构。第一栅极结构和第二栅极结构被电介质区域分开。集成电路还包括具有与介电区域接触的第一表面，第一栅极结构和第二栅极结构的金属触点。

2. 发明申请

WO2018140195A1 SYSTEMS, METHODS, AND APPARATUS FOR IMPROVED FINFETS 审中-公开
公开(公告)号：WO2018140195A1
公开(公告)日：2018-08-02
申请号：PCT/US2018/012025
申请日：2018-01-02
申请人： QUALCOMM INCORPORATED
发明人： LIU, Yanxiang , YANG, Haining
IPC分类号： H01L29/66 , H01L29/78 , H01L21/8234
摘要： To avoid the problems associated with low density spin on dielectrics, some examples of the disclosure include a finFET with an oxide material having different densities. For example, one such finFET may include an oxide material located in a gap between adjacent fins, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material and wherein the first density is greater than the second density.

3. 发明申请

WO2018005763A1 FIN FIELD EFFECT TRANSISTOR (FINFET) COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) CIRCUITS EMPLOYING SINGLE AND DOUBLE DIFFUSION BREAKS FOR INCREASED PERFORMANCE 审中-公开
标题翻译： FIN场效应晶体管（鳍式场效应晶体管）互补金属氧化物半导体（CMOS）电路，采用单一和双重扩散性能，提高性能
公开(公告)号：WO2018005763A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/039941
申请日：2017-06-29
申请人： QUALCOMM INCORPORATED
发明人： YUAN, Jun , LIU, Yanxiang , RIM, Kern
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092 , H01L21/762
摘要： Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.
摘要翻译：公开了用于增加性能的具有单扩散和双扩散中断的鳍场效应晶体管（FET）（FinFET）互补金属氧化物半导体（CMOS）电路。在一个方面中，采用单扩散和双扩散中断的FinFET CMOS电路包括P型FinFET，其包括由半导体衬底形成并且对应于P型扩散区域的第一Fin。 FinFET CMOS电路包括N型FinFET，其包括由半导体衬底形成并且对应于N型扩散区域的第二Fin。为了电隔离P型FinFET，在P型FinFET的栅极的任一侧上的第一Fin中形成第一和第二单扩散断裂（SDB）隔离结构。为了电隔离N型FinFET，在N型FinFET的栅极的任一侧上的第二Fin中形成第一和第二双扩散断开（DDB）隔离结构。

4. 发明申请

WO2018052564A1 CONTACT FOR SEMICONDUCTOR DEVICE 审中-公开
标题翻译： SEMICONDUCTOR DEVICE的接点
公开(公告)号：WO2018052564A1
公开(公告)日：2018-03-22
申请号：PCT/US2017/045567
申请日：2017-08-04
申请人： QUALCOMM INCORPORATED
发明人： LIU, Yanxiang , YANG, Haining , SUH, Youseok , CHOI, Jihong , BAO, Junjing
IPC分类号： H01L21/768 , H01L23/485
CPC分类号： H01L23/535 , H01L21/76805 , H01L21/76831 , H01L21/76843 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266
摘要： A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.
摘要翻译：半导体器件可以包括与栅极相邻的源极/漏极接触沟槽。源极/漏极接触沟槽可以包括第一部分上的第一部分和第二部分。半导体器件还可以包括在源极/漏极接触沟槽内的绝缘接触隔离体衬垫。绝缘接触隔离物衬里接触源极/漏极接触沟槽的第一部分而不接触第二部分。半导体器件还可以包括绝缘接触隔离物衬里内的导电材料以及源极/漏极接触沟槽的第二部分。导电材料可以落在半导体器件的源极/漏极区域中。

5. 发明申请

WO2016122882A1 OFF-CENTER GATE CUT 审中-公开
标题翻译：非中心门切割
公开(公告)号：WO2016122882A1
公开(公告)日：2016-08-04
申请号：PCT/US2016/013214
申请日：2016-01-13
申请人： QUALCOMM INCORPORATED
发明人： LIU, Yanxiang , SONG, Stanley, Seungchul
IPC分类号： H01L27/02 , H01L27/092
CPC分类号： H01L27/092 , H01L21/823828 , H01L21/823871 , H01L27/0207 , H01L29/0847
摘要： A semiconductor device includes a diffusion area, a gate structure coupled to the diffusion area, and a dummy gate structure coupled to the diffusion area. The gate structure extends a first distance beyond the diffusion area, and the dummy gate structure extends a second distance beyond the diffusion area.
摘要翻译：半导体器件包括扩散区域，耦合到扩散区域的栅极结构以及耦合到扩散区域的虚拟栅极结构。栅极结构延伸超过扩散区域的第一距离，并且虚拟栅极结构延伸超过扩散区域的第二距离。

6. 发明公开

EP3326198A1 DEVICE AND METHOD TO CONNECT GATE REGIONS SEPARATED USING A GATE CUT 审中-公开
公开(公告)号：EP3326198A1
公开(公告)日：2018-05-30
申请号：EP16745929.6
申请日：2016-07-08
申请人： Qualcomm Incorporated
发明人： LIU, Yanxiang , SONG, Stanley Seungchul , RIM, Kern
IPC分类号： H01L21/8238 , H01L27/02 , H01L27/092
CPC分类号： H01L29/4238 , G06F17/5077 , H01L21/3043 , H01L21/823821 , H01L21/823828 , H01L21/823871 , H01L23/5386 , H01L27/0207 , H01L27/092 , H01L27/0924 , H01L29/6681
摘要： A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further includes depositing a conductive material to form a conductive jumper structure to connect the first gate region and the second gate region.

7. 发明公开

EP3311405A1 STRUCTURE AND METHOD FOR TUNABLE MEMORY CELLS INCLUDING FIN FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：包括鳍场效应晶体管的可读存储器单元的结构和方法
公开(公告)号：EP3311405A1
公开(公告)日：2018-04-25
申请号：EP16730961.6
申请日：2016-06-06
申请人： Qualcomm Incorporated
发明人： YANG, Haining , LIU, Yanxiang
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L29/78 , H01L27/088 , H01L27/092 , H01L27/11 , H01L27/12
CPC分类号： H01L21/02 , G05B19/418 , G05B2219/45031 , H01L21/76895 , H01L21/823431 , H01L21/823821 , H01L21/845 , H01L27/0207 , H01L27/0886 , H01L27/0924 , H01L27/11 , H01L27/1104 , H01L27/1211 , H01L29/785
摘要： In a particular aspect, an integrated circuit includes a first gate structure coupled to a first fin field effect transistor (FinFET) device. The integrated circuit includes a second gate structure coupled to a second FinFET device. The first gate structure and the second gate structure are separated by a dielectric region. The integrated circuit further includes a metal contact having a first surface that is in contact with the dielectric region, the first gate structure, and the second gate structure.

8. 发明申请

WO2018057243A1 LAYOUT EFFECT MITIGATION IN FINFET 审中-公开
标题翻译： FINFET布局效应缓解
公开(公告)号：WO2018057243A1
公开(公告)日：2018-03-29
申请号：PCT/US2017/048841
申请日：2017-08-28
申请人： QUALCOMM INCORPORATED
发明人： YANG, Da , LIU, Yanxiang , YUAN, Jun , RIM, Kern
IPC分类号： H01L29/66 , H01L29/78
摘要： Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.
摘要翻译：描述了减轻布局效应的多栅极器件和制造方法。在用于制造诸如FinFET器件的多栅极半导体器件的常规工艺中，可以使用长隔离切割掩膜。这可能会导致不希望的布局效果。为了减轻或消除布局效应，提出了制造方法，其中层间电介质（ILD）层在制造过程期间在栅极切割位置保持完整。

9. 发明申请

WO2017184695A1 ESD DIODE, METHOD OF MANUFACTURING THE DIODE AND ESD CIRCUIT COMPRISING THE DIODE 审中-公开
标题翻译： ESD二极管，制造二极管的方法和包含该二极管的ESD电路
公开(公告)号：WO2017184695A1
公开(公告)日：2017-10-26
申请号：PCT/US2017/028298
申请日：2017-04-19
申请人： QUALCOMM INCORPORATED
发明人： LIU, Yanxiang , YANG, Haining , BAO, Junjing
IPC分类号： H01L27/02 , H01L29/06 , H01L29/66 , H01L29/861
CPC分类号： H01L27/0255 , H01L29/0646 , H01L29/0649 , H01L29/66128 , H01L29/66545 , H01L29/8611
摘要： Aspects for forming a self-aligned single diffusion break (SDB) isolation structure in a gate region of a diode for reduced capacitance, resistance, and/or area are disclosed.In one aspect, a diode is provided that includes a semiconductor substrate having a well region.P-doped and N-doped diffusion regions are formed in the well region of the semiconductor substrate.A self-aligned SDB isolation structure is formed in and self-aligned with a gate region between the P-doped and N-doped diffusion regions that electrically isolates such regions.The self-aligned SDB isolation structure reduces the parasitic capacitance of the diode compared to diodes having conductive gate structures in the gate region. The self-aligned SDB isolation structure has a width that reduces the length of a discharge path compared to conventional diodes, which reduces on-state resistance of the diode.
摘要翻译：公开了用于降低电容，电阻和/或面积的用于在二极管的栅极区中形成自对准单扩散中断（SDB）隔离结构的方面。一方面，二极管是条件是包括具有阱区的半导体衬底。在半导体衬底的阱区中形成P掺杂和N掺杂扩散区。自对准SDB隔离结构形成在半导体衬底的栅极区域中并与栅极区域自对准与这些区域电隔离的P掺杂和N掺杂扩散区域。与栅极区域中具有导电栅极结构的二极管相比，自对准SDB隔离结构减少了二极管的寄生电容。与传统二极管相比，自对准SDB隔离结构具有减小放电路径长度的宽度，这减小了二极管的导通电阻。

10. 发明申请

WO2017048405A1 TRANSISTOR TEMPERATURE SENSING 审中-公开
标题翻译：晶体管温度传感
公开(公告)号：WO2017048405A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/046045
申请日：2016-08-08
申请人： QUALCOMM INCORPORATED
发明人： LIU, Yanxiang , YANG, Haining , RIM, Kern
IPC分类号： G01K7/01 , H01L29/786
CPC分类号： G01K7/015 , H01L27/0924 , H01L29/78606
摘要： A device includes a source contact, a drain contact, a gate contact, and a body contact. The body contact is electrically coupled to a temperature sensing circuit. The source contact, the drain contact, the gate contact, and the body contact are included in a fin field-effect transistor (finFET).
摘要翻译：器件包括源极接触，漏极接触，栅极接触和身体接触。身体接触件电耦合到温度感测电路。源极接触，漏极接触，栅极接触和体接触包括在鳍状场效应晶体管（finFET）中。

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