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1. 发明专利

JP2010282637A Digital signal processor 有权
标题翻译：数字信号处理器
公开(公告)号：JP2010282637A
公开(公告)日：2010-12-16
申请号：JP2010157075
申请日：2010-07-09
申请人： Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人： SIH GILBERT C , ZOU QUIZHEN , JHA SANJAY K , KANG INYUP , LIN JIAN , MOTIWALA QUAEED , JOHN DEEPU , ZHANG LI , ZHANG HAITAO , LEE WAY-SHING , SAKAMAKI CHARLES E , KANTAK PRASHANT A
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F12/08 , G06F13/16 , G06F15/78
CPC分类号： G06F12/0886 , G06F9/30036 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/3816 , G06F9/3885 , G06F9/3893 , G06F15/7807
摘要： PROBLEM TO BE SOLVED: To provide a digital signal processor which enhances performance and availability. SOLUTION: A DSP includes a set of three data buses over which data may be exchanged with a register bank 120 and three data memories 102, 103 and 104. The register bank 120 may be used that includes registers accessible by at least two processing units 128 and 130. An instruction fetch unit 156 may include that receives instructions of variable length stored in an instruction memory 152. The instruction memory 152 may be separated from the set of three data memories 102, 103 and 104. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高性能和可用性的数字信号处理器。解决方案：DSP包括一组三条数据总线，数据可以通过该组三个数据总线与寄存器组120和三个数据存储器102,103和104进行交换。可以使用寄存器组120，其包括可由至少两个处理单元128和130.指令提取单元156可以包括接收存储在指令存储器152中的可变长度的指令。指令存储器152可以与三组数据存储器102,103和104分离。：（C）2011，JPO＆INPIT

2. 发明申请

WO0167621A3 TRANSMITTER ARCHITECTURES FOR COMMUNICATIONS SYSTEMS 审中-公开
标题翻译：用于通信系统的发射机结构
公开(公告)号：WO0167621A3
公开(公告)日：2002-05-02
申请号：PCT/US0106740
申请日：2001-03-02
申请人： QUALCOMM INC
发明人： YOUNIS SAED , SIMIC EMILIJA , WILBORN THOMAS , ZHANG HAITAO , FILIPOVIC DANIEL , KAUFMAN RALPH , LIN JIAN
IPC分类号： H04B1/04 , H03G3/20 , H03G3/30 , H04B7/005 , H04B7/24
CPC分类号： H03G3/3042 , H03F2203/7239 , H03G1/0088
摘要： Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.
摘要翻译：用于具有比传统发射机架构更好的性能的通信系统的发射机架构。这些改进包括以下组合：控制信号的响应时间更快，线性度更好，干扰减少，功耗降低，电路复杂度降低，成本降低。对于蜂窝应用，这些改进可以导致系统容量增加，电话尺寸更小，通话和待机时间增加，以及对产品的更多接受。提供电路以加快控制信号的响应时间。发送信号路径中的各种元件的控制回路被集成。增益控制机制允许精确调整输出发射功率电平。提供控制机制以在不需要时将功率放大器或全部发射信号路径断电。控制发射信号路径中的各种元件的增益以减少输出发射功率的瞬变，并且还确保瞬变向下。

3. 发明专利

DK1066559T3 未知
公开(公告)号：DK1066559T3
公开(公告)日：2005-10-03
申请号：DK99911150
申请日：1999-03-04
申请人： QUALCOMM INC
发明人： SIH GILBERT C , ZOU QUIZHEN , JHA SANJAY K , KANG INYUP , LIN JIAN , MOTIWALA QUAEED , JOHN DEEPU , ZHANG LI , ZHANG HAITAO , LEE WAY-SHING , SAKAMAKI CHARLES E , KANTAK PRASHANT A
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F12/08 , G06F12/0886 , G06F15/78
摘要： A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).

4. 发明专利

AU2003217857A1 HDLC HARDWARE ACCELERATOR 未知
公开(公告)号：AU2003217857A1
公开(公告)日：2003-09-09
申请号：AU2003217857
申请日：2003-02-27
申请人： QUALCOMM INC
发明人： ABROL NISCHAL , LIN JIAN , PAN HANFANG , TURNER SIMON
IPC分类号： H04L29/06 , H04L29/08
摘要： An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, “un-escaping” the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

5. 发明专利

ZA992157B A digital signal processor. 未知
公开(公告)号：ZA992157B
公开(公告)日：2000-07-07
申请号：ZA992157
申请日：1999-03-17
申请人： QUALCOMM INC
发明人： SIH GILBERT C , ZOU QIUZHEN , JHA SANJAY K , KANG INYUP , LIN JIAN , QUAEED SAKAMAKI MOTIWALA , JOHN DEEPU , ZHANG LI , ZHANG HAITAO , LEE WAY-SHING , SAKAMAKI CHARLES E , KANTAK PRASHANT A
IPC分类号： G06F20060101 , G11C20060101 , G06F , G11C

6. 发明专利

ZA9902157B A digital signal processor. 未知
公开(公告)号：ZA9902157B
公开(公告)日：2000-07-07
申请号：ZA9902157
申请日：1999-03-17
申请人： QUALCOMM INC
发明人： SIH GILBERT C , ZOU QIUZHEN , JHA SANJAY K , KANG INYUP , LIN JIAN , QUAEED SAKAMAKI MOTIWALA , JOHN DEEPU , ZHANG LI , ZHANG HAITAO , LEE WAY-SHING , SAKAMAKI CHARLES E , KANTAK PRASHANT A
IPC分类号： G06F20060101 , G11C20060101 , G06F , G11C

7. 发明专利

ES2356515T3 ARQUITECTURAS DE TRANSMISOR PARA SISTEMAS DE COMUNICACIONES. 未知
公开(公告)号：ES2356515T3
公开(公告)日：2011-04-08
申请号：ES07110669
申请日：2001-03-02
申请人： QUALCOMM INC
发明人： YOUNIS SAED , SIMIC EMILIJA , WILBORN THOMAS , ZHANG HAITAO , FILIPOVIC DANIEL , KAUFMAN RALPH , LIN JIAN
IPC分类号： H03G3/30 , H03G1/00 , H04B1/04 , H03G3/20 , H04B1/00 , H04B7/005 , H04B7/24
摘要： Un procedimiento para ajustar la ganancia de señal en un transmisor con un primer elemento de ganancia y un segundo elemento de ganancia, en el cual el primer elemento de ganancia responde a un primer reloj de actualización y el segundo elemento de ganancia responde a un segundo reloj de actualización, en el que el segundo reloj de actualización es más rápido que el primer reloj de actualización y los relojes de actualización primero y segundo son asíncronos, comprendiendo el procedimiento: recibir un primer valor de configuración de ganancia para el primer elemento de ganancia y un segundo valor de configuración de ganancia para el segundo elemento de ganancia; generar una primera señal de control de ganancia, representativa del primer valor de configuración de ganancia; generar una segunda señal de control de ganancia, representativa del segundo valor de configuración de ganancia; alinear la primera señal de control de ganancia con el primer reloj de actualización, y ajustar la ganancia del primer elemento de ganancia en un primer momento de actualización; detectar un cambio en el valor de configuración de ganancia del primer elemento de ganancia; si se detecta un cambio en el valor de configuración de ganancia, alinear la segunda señal de control de ganancia con el primer reloj de actualización, para ajustar la ganancia del segundo elemento de ganancia en el primer momento de actualización; si no se detecta ningún cambio en el valor de configuración de ganancia, alinear la segunda señal de control de ganancia con el segundo reloj de actualización; ajustar una ganancia del primer elemento de ganancia con la primera señal alineada de control de ganancia; y ajustar una ganancia del segundo elemento de ganancia con la segunda señal alineada de control de ganancia.

8. 发明专利

AU2010214743A1 Transmitter architectures for communications systems 未知
公开(公告)号：AU2010214743A1
公开(公告)日：2010-09-23
申请号：AU2010214743
申请日：2010-08-31
申请人： QUALCOMM INC
发明人： KAUFMAN RALPH , ZHANG HAITAO , YOUNIS SAED G , WILBORN THOMAS , FILIPOVIC DANIEL , LIN JIAN , SIMIC EMILIJA
IPC分类号： H03G3/30 , H04B1/04 , H03G3/20 , H04B7/005 , H04B7/24
摘要： Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

9. 发明专利

AT448602T 未知
公开(公告)号：AT448602T
公开(公告)日：2009-11-15
申请号：AT01916349
申请日：2001-03-02
申请人： QUALCOMM INC
发明人： YOUNIS SAED , SIMIC EMILIJA , WILBORN THOMAS , ZHANG HAITAO , FILIPOVIC DANIEL , KAUFMAN RALPH , LIN JIAN
IPC分类号： H04B1/00 , H04B1/04 , H03G3/20 , H03G3/30 , H04B7/005 , H04B7/24
摘要： Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

10. 发明专利

AU2008200624A1 Transmitter architectures for communications systems 未知
公开(公告)号：AU2008200624A1
公开(公告)日：2008-03-06
申请号：AU2008200624
申请日：2008-02-08
申请人： QUALCOMM INC
发明人： FILIPOVIC DANIEL , KAUFMAN RALPH , YOUNIS SAED G , WILBORN THOMAS , LIN JIAN , ZHANG HAITAO , SIMIC EMILIJA
IPC分类号： H03G3/30 , H04B1/04 , H03G3/20 , H04B7/005 , H04B7/24
摘要： Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

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