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    • 2. 发明授权
    • Programmable SFP or SFP+ module
    • 可编程SFP或SFP +模块
    • US08462838B2
    • 2013-06-11
    • US12631271
    • 2009-12-04
    • Qinghua ChenMaurilio De NicoloStephen OngRichard BrooksLiming Yin
    • Qinghua ChenMaurilio De NicoloStephen OngRichard BrooksLiming Yin
    • H03K5/159
    • H04L25/03038
    • Various example embodiments are disclosed. According to one example embodiment, a small form factor pluggable (SFP or SFP+) module may include an equalizer and a logic controller. The equalizer may be configured to receive data, provide signal information to a logic controller based on the received data, equalize the data based on equalization instructions received from the logic controller, and transmit the equalized data. The logic controller may be configured to transmit the signal information received from the equalizer receive programming instructions provide the equalization instructions to the equalizer based on the programming instructions, receive control inputs associated with the data, and provide status outputs based on the control inputs and the programming instructions. The SFP or SFP+ module may be configured to plug into a small form factor (SFF) host connector.
    • 公开了各种示例性实施例。 根据一个示例性实施例,小型可插拔(SFP或SFP +)模块可以包括均衡器和逻辑控制器。 均衡器可以被配置为接收数据,基于接收到的数据向逻辑控制器提供信号信息,基于从逻辑控制器接收的均衡指令来均衡数据,并发送均衡的数据。 逻辑控制器可以被配置为发送从均衡器接收的信号信息,接收编程指令基于编程指令向均衡器提供均衡指令,接收与数据相关联的控制输入,并且基于控制输入和 编程说明。 SFP或SFP +模块可以配置为插入小型(SFF)主机连接器。
    • 3. 发明授权
    • Duty cycle optimized prescaler
    • 占空比优化预分频器
    • US06268751B1
    • 2001-07-31
    • US09454933
    • 1999-12-03
    • Qinghua ChenKhodor ElnasharKishore Mishra
    • Qinghua ChenKhodor ElnasharKishore Mishra
    • H03K3017
    • H03K21/08
    • A Duty cycle optimized prescaler (10) optimizes the clock duty cycle as close as possible to fifty percent. This is achieved by employing two count by two counters (11,12), one (12)to count negative edges of the clock pulse, and one (11)to count positive edges of the clock pulse. Each counter (11,12) output is connected to a comparator (14,15) which compares each counter output (11,12)to a prescaler setting (13). The comparators (14,15) outputs are input to an OR gate (16), the output of which, when, a logic 1, resets the counters(11,12) and toggles a flip-flop circuit (17) providing a clock output signal.
    • 一个占空比优化的预分频器(10)将时钟占空比最优化到最接近50%。 这通过采用两个计数器(11,12)计数,一个(12)计数时钟脉冲的负沿,以及一个(11)计数时钟脉冲的正边沿来实现。 每个计数器(11,12)输出连接到比较器(14,15),比较器将每个计数器输出(11,12)与预分频器设置(13)进行比较。 比较器(14,15)输出被输入到或门(16),其输出当逻辑1复位计数器(11,12)时,切换提供时钟的触发器电路(17) 输出信号。
    • 5. 发明申请
    • PROGRAMMABLE SFP OR SFP+ MODULE
    • 可编程SFP或SFP +模块
    • US20110134988A1
    • 2011-06-09
    • US12631271
    • 2009-12-04
    • Qinghua ChenMaurilio De NicoloStephen OngRichard BrooksLiming Yin
    • Qinghua ChenMaurilio De NicoloStephen OngRichard BrooksLiming Yin
    • H03H7/30
    • H04L25/03038
    • Various example embodiments are disclosed. According to one example embodiment, a small form factor pluggable (SFP or SFP+) module may include an equalizer and a logic controller. The equalizer may be configured to receive data, provide signal information to a logic controller based on the received data, equalize the data based on equalization instructions received from the logic controller, and transmit the equalized data. The logic controller may be configured to transmit the signal information received from the equalizer receive programming instructions provide the equalization instructions to the equalizer based on the programming instructions, receive control inputs associated with the data, and provide status outputs based on the control inputs and the programming instructions. The SFP or SFP+ module may be configured to plug into a small form factor (SFF) host connector.
    • 公开了各种示例性实施例。 根据一个示例性实施例,小型可插拔(SFP或SFP +)模块可以包括均衡器和逻辑控制器。 均衡器可以被配置为接收数据,基于接收到的数据向逻辑控制器提供信号信息,基于从逻辑控制器接收的均衡指令来均衡数据,并发送均衡的数据。 逻辑控制器可以被配置为发送从均衡器接收的信号信息,接收编程指令基于编程指令向均衡器提供均衡指令,接收与数据相关联的控制输入,并且基于控制输入和 编程说明。 SFP或SFP +模块可以配置为插入小型(SFF)主机连接器。