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1. 发明申请

US20060220173A1 Wafer level package including a device wafer integrated with a passive component 有权
公开(公告)号：US20060220173A1
公开(公告)日：2006-10-05
申请号：US11097646
申请日：2005-04-01
申请人： Qing Gan , Robert Warren , Anthony Lobianco , Steve Liang
发明人： Qing Gan , Robert Warren , Anthony Lobianco , Steve Liang
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L23/49822 , B81C1/00269 , H01L21/4857 , H01L21/6835 , H01L23/49816 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2221/68327 , H01L2221/68345 , H01L2224/0401 , H01L2224/04026 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/1146 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/16235 , H01L2224/2746 , H01L2224/29011 , H01L2224/291 , H01L2224/29109 , H01L2224/29111 , H01L2224/29144 , H01L2224/32235 , H01L2224/73103 , H01L2224/81005 , H01L2224/81192 , H01L2224/81801 , H01L2224/83005 , H01L2224/83192 , H01L2224/9211 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/14 , H01L2924/1461 , H01L2924/15151 , H01L2924/15159 , H01L2924/15184 , H01L2924/15311 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2924/01047 , H01L2924/01029 , H01L2924/0105 , H01L2224/81 , H01L2224/83 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.

2. 发明申请

US20080003761A1 Method for fabricating a wafer level package with device wafer and passive component integration 有权
标题翻译：用于制造具有器件晶片和无源部件集成的晶片级封装的方法
公开(公告)号：US20080003761A1
公开(公告)日：2008-01-03
申请号：US11899926
申请日：2007-09-07
申请人： Qing Gan , Robert Warren , Anthony Lobianco , Steve Liang
发明人： Qing Gan , Robert Warren , Anthony Lobianco , Steve Liang
IPC分类号： H01L21/20
CPC分类号： H01L23/49822 , B81C1/00269 , H01L21/4857 , H01L21/6835 , H01L23/49816 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2221/68327 , H01L2221/68345 , H01L2224/0401 , H01L2224/04026 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/1146 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/16235 , H01L2224/2746 , H01L2224/29011 , H01L2224/291 , H01L2224/29109 , H01L2224/29111 , H01L2224/29144 , H01L2224/32235 , H01L2224/73103 , H01L2224/81005 , H01L2224/81192 , H01L2224/81801 , H01L2224/83005 , H01L2224/83192 , H01L2224/9211 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/14 , H01L2924/1461 , H01L2924/15151 , H01L2924/15159 , H01L2924/15184 , H01L2924/15311 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2924/01047 , H01L2924/01029 , H01L2924/0105 , H01L2224/81 , H01L2224/83 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.
摘要翻译：根据示例性实施例，晶片级封装包括包括至少一个器件晶片接触焊盘和器件的器件晶片，并且其中所述至少一个器件晶片接触焊盘电连接到所述器件。晶片级封装包括位于器件晶片上方的第一聚合物层。晶片级封装包括位于第一聚合物层之上并具有第一端子和第二端子的至少一个无源部件。所述至少一个无源部件的第一端子电连接到所述至少一个器件晶片接触焊盘。晶片级封装包括位于至少一个无源部件上的第二聚合物层。晶片级封装包括位于第二聚合物层之上并电连接至至少一个无源元件的第二端子的至少一个聚合物层接触焊盘。

3. 发明申请

US20060211233A1 Method for fabricating a wafer level package having through wafer vias for external package connectivity and related structure 审中-公开
标题翻译：用于制造具有通过用于外部封装连接和相关结构的晶片通孔的晶片级封装的方法
公开(公告)号：US20060211233A1
公开(公告)日：2006-09-21
申请号：US11085968
申请日：2005-03-21
申请人： Qing Gan , Anthony Lobianco , Robert Warren
发明人： Qing Gan , Anthony Lobianco , Robert Warren
IPC分类号： H01L21/44
CPC分类号： B81C1/00301 , B81B2207/095 , H01L23/10 , H01L23/3114 , H01L2924/0002 , H01L2924/01079 , H01L2924/00
摘要： According to an exemplary embodiment, a method for fabricating a wafer level package includes forming a polymer layer on a device wafer, where the device wafer includes at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The method further includes bonding a protective wafer to the device wafer. The method further includes forming at least one via in the protective wafer, where the at least one via extends through the protective wafer and is situated over the at least one device wafer contact pad. The method further includes forming at least one protective wafer contact pad on the protective wafer, where the at least one protective wafer contact pad is situated over the at least one via and electrically connected to the at least one device wafer contact pad.
摘要翻译：根据示例性实施例，用于制造晶片级封装的方法包括在器件晶片上形成聚合物层，其中器件晶片包括至少一个器件晶片接触焊盘和器件，并且其中至少一个器件晶片接触焊盘电连接到设备。该方法还包括将保护晶片接合到器件晶片。该方法还包括在保护晶片中形成至少一个通孔，其中至少一个通孔延伸穿过保护晶片并且位于至少一个器件晶片接触焊盘上方。所述方法还包括在所述保护晶片上形成至少一个保护性晶片接触焊盘，其中所述至少一个保护性晶片接触焊盘位于所述至少一个通孔上并电连接至所述至少一个器件晶片接触焊盘。

4. 发明授权

US07696064B2 Methods for forming a through via 有权
标题翻译：形成通孔的方法
公开(公告)号：US07696064B2
公开(公告)日：2010-04-13
申请号：US11870624
申请日：2007-10-11
申请人： Qing Gan , Anthony LoBianco
发明人： Qing Gan , Anthony LoBianco
IPC分类号： H01L21/46 , H01L21/302
CPC分类号： H01L21/76898 , B81C1/00095 , B81C1/00238 , H01L24/11 , H01L2224/05001 , H01L2224/05009 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/056 , H01L2924/14 , H01L2924/1461 , H01L2924/00 , H01L2924/00014
摘要： A through via is constructed in a two-stage process. A void in a portion of the depth of the substrate is filled from a first surface of the semiconductor substrate creating an enclosed volume within the substrate. Thereafter, the enclosed volume is exposed and the remaining portion of the void is filled.
摘要翻译： A通孔在两级过程中构建。在半导体衬底的第一表面上填充衬底的深度的一部分中的空隙，从而在衬底内产生封闭的体积。此后，封闭的体积被暴露，空隙的剩余部分被填充。

5. 发明申请

US20090098731A1 Methods for Forming a Through Via 有权
标题翻译：形成通过的方法
公开(公告)号：US20090098731A1
公开(公告)日：2009-04-16
申请号：US11870624
申请日：2007-10-11
申请人： Qing Gan , Anthony LoBianco
发明人： Qing Gan , Anthony LoBianco
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , B81C1/00095 , B81C1/00238 , H01L24/11 , H01L2224/05001 , H01L2224/05009 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/056 , H01L2924/14 , H01L2924/1461 , H01L2924/00 , H01L2924/00014
摘要： A through via is constructed in a two-stage process. A void in a portion of the depth of the substrate is filled from a first surface of the semiconductor substrate creating an enclosed volume within the substrate. Thereafter, the enclosed volume is exposed and the remaining portion of the void is filled.
摘要翻译： A通孔在两级过程中构建。在半导体衬底的第一表面上填充衬底的深度的一部分中的空隙，从而在衬底内产生封闭的体积。此后，封闭的体积被暴露，空隙的剩余部分被填充。

6. 发明授权

US06787897B2 Wafer-level package with silicon gasket 有权
公开(公告)号：US06787897B2
公开(公告)日：2004-09-07
申请号：US10028058
申请日：2001-12-20
申请人： Frank S Geefay , Qing Gan , Ann Mattos , Domingo A Figueredo
发明人： Frank S Geefay , Qing Gan , Ann Mattos , Domingo A Figueredo
IPC分类号： H01L2348
CPC分类号： B81B7/0077 , H01L21/50 , H01L23/10 , H01L2924/0002 , H01L2924/01079 , H01L2924/09701 , H01L2924/00
摘要： A gasket encloses a hermetically sealed environment between a cap wafer and a base wafer. The gasket is bonded to the base wafer using bonding material. The bonding material can be one or more of many substances that exhibit acceptable adhesion, sealing, and other properties that ensure a hermetically sealed environment. The gasket is carved out from the cap wafer material itself. The cap wafer is typically made of extremely strong and rigid material such as silicon. Since the gasket is made from the cap wafer, the gasket itself is also extremely strong and rigid.

7. 发明授权

US07629201B2 Method for fabricating a wafer level package with device wafer and passive component integration 有权
标题翻译：用于制造具有器件晶片和无源部件集成的晶片级封装的方法
公开(公告)号：US07629201B2
公开(公告)日：2009-12-08
申请号：US11899926
申请日：2007-09-07
申请人： Qing Gan , Robert W. Warren , Anthony J. Lobianco , Steve X. Liang
发明人： Qing Gan , Robert W. Warren , Anthony J. Lobianco , Steve X. Liang
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L23/49822 , B81C1/00269 , H01L21/4857 , H01L21/6835 , H01L23/49816 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2221/68327 , H01L2221/68345 , H01L2224/0401 , H01L2224/04026 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/1146 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/16235 , H01L2224/2746 , H01L2224/29011 , H01L2224/291 , H01L2224/29109 , H01L2224/29111 , H01L2224/29144 , H01L2224/32235 , H01L2224/73103 , H01L2224/81005 , H01L2224/81192 , H01L2224/81801 , H01L2224/83005 , H01L2224/83192 , H01L2224/9211 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/14 , H01L2924/1461 , H01L2924/15151 , H01L2924/15159 , H01L2924/15184 , H01L2924/15311 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2924/01047 , H01L2924/01029 , H01L2924/0105 , H01L2224/81 , H01L2224/83 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.
摘要翻译：根据示例性实施例，晶片级封装包括包括至少一个器件晶片接触焊盘和器件的器件晶片，并且其中所述至少一个器件晶片接触焊盘电连接到所述器件。晶片级封装包括位于器件晶片上方的第一聚合物层。晶片级封装包括位于第一聚合物层之上并具有第一端子和第二端子的至少一个无源部件。所述至少一个无源部件的第一端子电连接到所述至少一个器件晶片接触焊盘。晶片级封装包括位于至少一个无源部件上的第二聚合物层。晶片级封装包括位于第二聚合物层之上并电连接至至少一个无源元件的第二端子的至少一个聚合物层接触焊盘。

8. 发明授权

US07576426B2 Wafer level package including a device wafer integrated with a passive component 有权
标题翻译：晶圆级封装，包括与无源元件集成的器件晶片
公开(公告)号：US07576426B2
公开(公告)日：2009-08-18
申请号：US11097646
申请日：2005-04-01
申请人： Qing Gan , Robert W. Warren , Anthony J. Lobianco , Steve X. Liang
发明人： Qing Gan , Robert W. Warren , Anthony J. Lobianco , Steve X. Liang
IPC分类号： H01L23/10 , H01L23/48
CPC分类号： H01L23/49822 , B81C1/00269 , H01L21/4857 , H01L21/6835 , H01L23/49816 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2221/68327 , H01L2221/68345 , H01L2224/0401 , H01L2224/04026 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/1146 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/16235 , H01L2224/2746 , H01L2224/29011 , H01L2224/291 , H01L2224/29109 , H01L2224/29111 , H01L2224/29144 , H01L2224/32235 , H01L2224/73103 , H01L2224/81005 , H01L2224/81192 , H01L2224/81801 , H01L2224/83005 , H01L2224/83192 , H01L2224/9211 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/14 , H01L2924/1461 , H01L2924/15151 , H01L2924/15159 , H01L2924/15184 , H01L2924/15311 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2924/01047 , H01L2924/01029 , H01L2924/0105 , H01L2224/81 , H01L2224/83 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： According to an exemplary embodiment, a wafer level package includes a device wafer including at least one device wafer contact pad and a device, and where the at least one device wafer contact pad is electrically connected to the device. The wafer level package includes a first polymer layer situated over the device wafer. The wafer level package includes at least one passive component situated over the first polymer layer and having a first terminal and a second terminal. The first terminal of the at least one passive component is electrically connected to the at least one device wafer contact pad. The wafer level package includes a second polymer layer situated over the at least one passive component. The wafer level package includes at least one polymer layer contact pad situated over the second polymer layer and electrically connected to the second terminal of the at least one passive component.
摘要翻译：根据示例性实施例，晶片级封装包括包括至少一个器件晶片接触焊盘和器件的器件晶片，并且其中所述至少一个器件晶片接触焊盘电连接到所述器件。晶片级封装包括位于器件晶片上方的第一聚合物层。晶片级封装包括位于第一聚合物层之上并具有第一端子和第二端子的至少一个无源部件。所述至少一个无源部件的第一端子电连接到所述至少一个器件晶片接触焊盘。晶片级封装包括位于至少一个无源部件上的第二聚合物层。晶片级封装包括位于第二聚合物层之上并电连接至至少一个无源元件的第二端子的至少一个聚合物层接触焊盘。

9. 发明授权

US06979597B2 Wafer-level package with silicon gasket 有权
标题翻译：晶圆级封装带硅垫片
公开(公告)号：US06979597B2
公开(公告)日：2005-12-27
申请号：US10615672
申请日：2003-07-08
申请人： Frank S Geefay , Qing Gan , Ann Mattos , Domingo A Figueredo
发明人： Frank S Geefay , Qing Gan , Ann Mattos , Domingo A Figueredo
IPC分类号： H01L23/02 , B81B7/00 , H01L21/50 , H01L23/10 , H01L21/44 , H01L21/30 , H01L21/46 , H01L21/48
CPC分类号： B81B7/0077 , H01L21/50 , H01L23/10 , H01L2924/0002 , H01L2924/01079 , H01L2924/09701 , H01L2924/00
摘要： A gasket encloses a hermetically sealed environment between a cap wafer and a base wafer. The gasket is bonded to the base wafer using bonding material. The bonding material can be one or more of many substances that exhibit acceptable adhesion, sealing, and other properties that ensure a hermetically sealed environment. The gasket is carved out from the cap wafer material itself. The cap wafer is typically made of extremely strong and rigid material such as silicon. Since the gasket is made from the cap wafer, the gasket itself is also extremely strong and rigid.
摘要翻译：垫圈在盖晶片和基底晶片之间包围密封的环境。垫圈使用接合材料结合到基底晶片。接合材料可以是显示可接受的粘合性，密封性和确保密封环境的其它性质的许多物质中的一种或多种。垫片从盖片材料本身雕刻出来。盖晶片通常由非常坚固和刚性的材料制成，例如硅。由于垫片由盖片制成，所以垫片本身也非常坚固和刚性。

10. 发明授权

US06763702B2 Method and apparatus for hermeticity determination and leak detection in semiconductor packaging 有权
标题翻译：用于半导体封装中的气密性测定和泄漏检测的方法和装置
公开(公告)号：US06763702B2
公开(公告)日：2004-07-20
申请号：US10325356
申请日：2002-12-19
申请人： Allen Chien , Frank S Geefay , Cheol Hyun Han , Qing Gan
发明人： Allen Chien , Frank S Geefay , Cheol Hyun Han , Qing Gan
IPC分类号： G01M316
CPC分类号： G01M3/226
摘要： A method and apparatus for determining the hermeticity of a semiconductor package is disclosed. Gas is introduced into the semiconductor package during packaging. Vacuum suction is then applied to the package. If the package has any leaks, the gas within will escape. The package is next scanned using a spectrometer. If the spectrometer does not detect any gas within the package cavity, the package is not hermetically sealed. In an alternate embodiment, the device is packaged first, and then immersed in a pressurized liquid. If the package has a leak, the pressure on the liquid will force liquid into the package cavity. The cavity of a properly sealed package will remain empty and dry. The package is scanned using a spectrometer. If the spectrometer detects liquid within the package, the package is not hermetically sealed.
摘要翻译：公开了一种用于确定半导体封装的气密性的方法和装置。在包装过程中将气体引入半导体封装。然后将真空吸力施加到包装上。如果包装有任何泄漏，内部的气体将会逸出。然后使用光谱仪扫描包装。如果光谱仪没有检测到封装腔内的任何气体，封装件不会被密封。在替代实施例中，装置首先包装，然后浸入加压液体中。如果包装有泄漏，液体上的压力将迫使液体进入包装腔。正确密封的包装的空腔将保持空且干燥。使用光谱仪扫描包装。如果光谱仪检测到包装内的液体，则封装不是密封的。

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