专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180042815A1 MULTI-FUNCTIONAL ELECTRO-SPOON NEEDLE THERAPEUTIC APPARATUS 审中-公开
公开(公告)号：US20180042815A1
公开(公告)日：2018-02-15
申请号：US15557133
申请日：2016-03-09
申请人： Qiang Tang , Luwen Zhu , Zhejiang Scobry Medical Technology Co., Ltd.
发明人： Qiang Tang , Luwen Zhu , Yan Wang , Yanli Xing , Zhishun Yu
IPC分类号： A61H39/04 , A61H39/00
摘要： Disclosed is a multi-functional electro-spoon needle therapeutic apparatus, which includes a top cover, locating pieces, a fixed lid, a rear cover, electro-spoon needles and an adjustment mechanism, wherein the locating pieces are respectively mounted on the top cover and the rear cover, and each locating piece is provided with a long groove; the fixed lid is respectively fixed on the top cover and the rear cover so as to respectively hold the locating pieces between the top cover and the fixed lid and between the rear cover and the fixed lid; the rear cover is arranged behind the top cover and connected to the top cover via the adjustment mechanism; and the electro-spoon needles are mounted in the long grooves of the locating pieces and can move along the long grooves. The apparatus has a simple structure, so a patient can perform acupuncture by himself.

2. 发明授权

US10478378B2 Multi-functional electro-spoon needle therapeutic apparatus 有权
公开(公告)号：US10478378B2
公开(公告)日：2019-11-19
申请号：US15557133
申请日：2016-03-09
申请人： Qiang Tang , Luwen Zhu , Zhejiang Scobry Medical Technology Co., Ltd.
发明人： Qiang Tang , Luwen Zhu , Yan Wang , Yanli Xing , Zhishun Yu
IPC分类号： A61N1/04 , A61H39/04 , A61N1/36 , A61H39/00 , A61H39/08 , A61H7/00
摘要： Disclosed is a multi-functional electro-spoon needle therapeutic apparatus, which includes a top cover, locating pieces, a fixed lid, a rear cover, electro-spoon needles and an adjustment mechanism, wherein the locating pieces are respectively mounted on the top cover and the rear cover, and each locating piece is provided with a long groove; the fixed lid is respectively fixed on the top cover and the rear cover so as to respectively hold the locating pieces between the top cover and the fixed lid and between the rear cover and the fixed lid; the rear cover is arranged behind the top cover and connected to the top cover via the adjustment mechanism; and the electro-spoon needles are mounted in the long grooves of the locating pieces and can move along the long grooves. The apparatus has a simple structure, so a patient can perform acupuncture by himself.

3. 发明授权

US08698555B2 Low distortion variable gain amplifier (VGA) 有权
标题翻译：低失真可变增益放大器（VGA）
公开(公告)号：US08698555B2
公开(公告)日：2014-04-15
申请号：US13291782
申请日：2011-11-08
申请人： Steve Fang , Qiang Tang , Myung Jae Yoo
发明人： Steve Fang , Qiang Tang , Myung Jae Yoo
IPC分类号： H03F1/02 , G11B5/09
CPC分类号： H03F3/45071 , H03F1/303 , H03F1/3211 , H03F3/45475 , H03F2200/234 , H03F2203/45116 , H03F2203/45588 , H03F2203/45591 , H03F2203/45594 , H03F2203/45616 , H03F2203/45618 , H03G1/0023 , H03G3/004
摘要： In one embodiment, an apparatus an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier, the input node receiving the asymmetric signal. A second resistance is coupled to the input node of the amplifier. The second resistance includes a linear resistor. A third resistance is coupled to the second resistance. The third resistance is varied to adjust an amount of asymmetric correction provided by the amplifier to correct the asymmetric signal at the output node. The amount of asymmetric correction is a function of the first resistance and a combination of the second resistance and the third resistance.
摘要翻译：在一个实施例中，一种被配置为接收不对称信号的放大器的装置。第一电阻耦合在放大器的输入节点和输出节点之间，输入节点接收不对称信号。第二电阻耦合到放大器的输入节点。第二个电阻包括一个线性电阻。第三电阻耦合到第二电阻。改变第三电阻以调整由放大器提供的非对称校正量，以校正输出节点处的不对称信号。非对称校正的量是第一电阻和第二电阻和第三电阻的组合的函数。

4. 发明授权

US08482039B1 Memory and interconnect design in fine pitch 有权
标题翻译：存储器和互连设计在细微间距
公开(公告)号：US08482039B1
公开(公告)日：2013-07-09
申请号：US13613680
申请日：2012-09-13
申请人： Qiang Tang , Min She , Ken Liao
发明人： Qiang Tang , Min She , Ken Liao
IPC分类号： H01L23/52
CPC分类号： H01L23/522 , H01L27/105 , H01L27/10882 , H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： A memory array includes a first layer, a second layer, a third layer and a contact. The first layer is disposed on a substrate. The second layer includes a first conductive line. The first conductive line includes first line segments and second line segments. Each of the second line segments are connected to a respective one of the first line segments. The first line segments extend in a first direction on the first layer. The second line segments extend in a second direction on the first layer. The first direction is different than the second direction. The third layer is disposed on the second layer. The contact is disposed through the second layer and connects the third layer to the first conductive line. One of the first line segments extends towards the contact. Each of the first and second line segments are at least a predetermined distance from the contact.
摘要翻译：存储器阵列包括第一层，第二层，第三层和接触层。第一层设置在基板上。第二层包括第一导电线。第一导线包括第一线段和第二线段。每个第二线段连接到第一线段中相应的一个。第一线段在第一层上沿第一方向延伸。第二线段在第一层上沿第二方向延伸。第一方向与第二方向不同。第三层设置在第二层上。接触件通过第二层设置，并将第三层连接到第一导电线。第一个线段之一延伸到联系人。第一和第二线段中的每一个至少距离接触件的预定距离。

5. 发明授权

US08378731B1 Asymmetric correction circuit with negative resistance 有权
标题翻译：具有负电阻的非对称校正电路
公开(公告)号：US08378731B1
公开(公告)日：2013-02-19
申请号：US13159241
申请日：2011-06-13
申请人： Qiang Tang , Bo Wang
发明人： Qiang Tang , Bo Wang
IPC分类号： H03L5/00
CPC分类号： H03G1/0029 , G11B20/10027 , G11B20/10324 , H03F3/45201 , H03F3/45475 , H03F2203/45396 , H03F2203/45522 , H03F2203/45562 , H03F2203/45591
摘要： In one embodiment, an apparatus includes an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier. A second resistance is coupled to the input node of the amplifier. A first switch is configured to be controlled during a first interval to couple the second resistance to a positive resistance to increase a gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the positive resistance. A second switch is configured to be controlled during a second interval to couple the second resistance to a negative resistance to decrease the gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the negative resistance.
摘要翻译：在一个实施例中，一种装置包括被配置为接收不对称信号的放大器。第一电阻耦合在放大器的输入节点和输出节点之间。第二电阻耦合到放大器的输入节点。第一开关被配置为在第一间隔期间被控制以将第二电阻耦合到正电阻以增加放大器的增益以校正不对称信号。增益是第一电阻和第二电阻和正电阻的组合的函数。第二开关被配置为在第二间隔期间被控制以将第二电阻耦合到负电阻以减小放大器的增益以校正不对称信号。增益是第一电阻和第二电阻和负电阻的组合的函数。

6. 发明授权

US08248848B1 System and methods for multi-level nonvolatile memory read, program and erase 有权
标题翻译：用于多级非易失性存储器读取，编程和擦除的系统和方法
公开(公告)号：US08248848B1
公开(公告)日：2012-08-21
申请号：US12240123
申请日：2008-09-29
申请人： Qiang Tang , Bo Wang , Chih-Hsin Wang
发明人： Qiang Tang , Bo Wang , Chih-Hsin Wang
IPC分类号： G11C16/04 , G11C7/06
CPC分类号： G11C16/3445 , G11C7/1006 , G11C11/56 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C2013/0076
摘要： A memory circuit includes a memory array with multi-level cells that are each capable of storing M bits of data, where M is an integer greater than one. A module reads a state of one of the multi-level cells. The module performs at least one of a first erase operation and a first program operation on the one of the multi-level cells for the M bits of data during a first time period.
摘要翻译：存储器电路包括具有多级单元的存储器阵列，每个单元能够存储M位数据，其中M是大于1的整数。模块读取多级单元之一的状态。该模块在第一时间段期间针对M位数据执行多级单元中的一个上的第一擦除操作和第一编程操作中的至少一个。

7. 发明申请

US20110006347A1 LAYOUT FOR HIGH DENSITY CONDUCTIVE INTERCONNECTS 有权
标题翻译：高密度导电互连布局
公开(公告)号：US20110006347A1
公开(公告)日：2011-01-13
申请号：US12830754
申请日：2010-07-06
申请人： Qiang Tang , Ramin Ghodsi
发明人： Qiang Tang , Ramin Ghodsi
IPC分类号： H01L27/118
CPC分类号： G11C7/18 , G11C2207/005
摘要： In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry.
摘要翻译：在本发明的一个实施例中，用于将多个位线连接到感测电路的方法包括提供从第一金属层中的存储器阵列延伸的多个位线。多个位线在第一金属层的第一区域中彼此间隔开平均间隔x。该方法还包括将多个位线的一部分升高到覆盖第一金属层的第二金属层。升高的位线在第二金属层中以平均间隔y彼此分开，y> x。该方法还包括将多个位线的一部分延伸到第一金属层的第二区域中。扩展位线在第一金属层的第二区域中的平均间隔z彼此分开，z> x。该方法还包括将第二金属层中的位线和第一金属层中的位线连接到感测电路。

8. 发明授权

US07821045B2 Apparatus, system, and method for multiple-segment floating gate 有权
标题翻译：多段浮栅的装置，系统及方法
公开(公告)号：US07821045B2
公开(公告)日：2010-10-26
申请号：US11617484
申请日：2006-12-28
申请人： Qiang Tang , Venkat Narayanan
发明人： Qiang Tang , Venkat Narayanan
IPC分类号： H01L29/80 , H01L21/8238
CPC分类号： H01L29/42324 , H01L21/28273 , H01L27/115 , H01L27/11521
摘要： Various embodiments include a substrate and a memory cell coupled to the substrate. The memory cell may include an L-shaped floating gate, a control gate, an insulation layer coupled between the control gate and the first L-shaped floating gate, and a conductive layer coupled between the substrate and the first L-shape floating gate. Other embodiments including additional apparatus, systems, and methods are disclosed.
摘要翻译：各种实施例包括基板和耦合到基板的存储单元。存储单元可以包括L形浮置栅极，控制栅极，耦合在控制栅极和第一L形浮置栅极之间的绝缘层，以及耦合在基板和第一L形浮动栅极之间的导电层。公开了包括附加装置，系统和方法的其它实施例。

9. 发明授权

US07697343B2 Circuit and method for pre-charging from both ends of an array in a read operation in NAND flash memory 有权
标题翻译：在NAND闪存中的读取操作中从阵列的两端预充电的电路和方法
公开(公告)号：US07697343B2
公开(公告)日：2010-04-13
申请号：US11862905
申请日：2007-09-27
申请人： Qiang Tang
发明人： Qiang Tang
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/26
摘要： A circuit for performing a read operation in a NAND flash memory is disclosed. The NAND flash memory includes an array of bit lines grouped into first group of bit lines and second group of bit lines. The circuit includes a plurality of pre-charging and reading circuitries connected at first end of the array of bit lines and a plurality of pre-charging circuitries connected at second end of the array of bit lines. The pre-charging and reading circuitries include a select circuit which selects one group from the first and the second group of bit lines; a first and a second circuit to pre-charge and read the selected group of bit lines from the first end. The plurality of pre-charging circuits include two select lines to select one group of bit lines, and a plurality of pre-charging transistors to pre-charge the selected group of bit lines from the second end.
摘要翻译：公开了一种用于在NAND闪速存储器中执行读取操作的电路。 NAND闪存包括分组成第一组位线和第二组位线的位线阵列。电路包括连接在位线阵列的第一端的多个预充电和读取电路以及连接在位线阵列的第二端的多个预充电电路。预充电和读取电路包括从第一组和第二组位线选择一组的选择电路; 第一和第二电路，用于从第一端预充电和读取所选择的位线组。多个预充电电路包括两条用于选择一组位线的选择线，以及多个预充电晶体管，用于从第二端预先选定所选择的一组位线。

10. 发明申请

US20080049518A1 NAND flash memory programming 有权
标题翻译： NAND闪存编程
公开(公告)号：US20080049518A1
公开(公告)日：2008-02-28
申请号：US11511038
申请日：2006-08-28
申请人： Ramin Ghodsi , Qiang Tang
发明人： Ramin Ghodsi , Qiang Tang
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/12
摘要： A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a control gate to a programming voltage, and floating the substrate channel voltage while the control gate is at the programming voltage. Memory devices include state machines or controllers operable to perform the described method, and operation of such a state machine, memory device, and information handling system are described.
摘要翻译：一种对非易失性存储单元中的浮置栅极进行充电的方法包括：使存储单元内的衬底沟道达到第一电压，使控制栅极达到编程电压，并且在控制栅极处于编程电压的同时浮置衬底沟道电压。存储器件包括可操作以执行所述方法的状态机或控制器，并描述了这种状态机，存储器件和信息处理系统的操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式