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1. 发明申请

US20130296929A1 HIGH-STRENGTH BIOLOGICAL SCAFFOLD MATERIAL AND PREPARATION METHOD THEREOF 审中-公开
标题翻译：高强度生物材料及其制备方法
公开(公告)号：US20130296929A1
公开(公告)日：2013-11-07
申请号：US13981256
申请日：2011-10-31
申请人： Qiang Lv , Zheng Luo
发明人： Qiang Lv , Zheng Luo
IPC分类号： A61F2/00
CPC分类号： A61F2/0009 , A61B17/12031 , A61L27/227 , A61L27/34 , A61L27/56 , C08L89/00
摘要： A high-strength biological scaffold and preparation method thereof. The biological scaffold is comprised of a framework of boiled-off silk woven material, the form of the framework is determined by actual needs; the framework surface is coated with a layer of silk protein scaffold material, fibroin protein/gelatin biological scaffold material or fibroin protein/collagen biological scaffold material having a thickness of 100 micrometers to 5 centimeters. The high-strength biological scaffold material has high tear resistance strength and mechanical strength and good biocompatibility, has a porous structure suitable for tissue regeneration, and can be used for preparing anal fistula repair plugs.
摘要翻译：一种高强度生物支架及其制备方法。生物支架由一个起绒丝织物的框架组成，框架的形式由实际需要决定; 框架表面涂覆有一层丝蛋白支架材料，丝心蛋白/明胶生物支架材料或具有100微米至5厘米厚度的丝心蛋白/胶原生物支架材料。高强度生物支架材料具有高抗撕裂强度和机械强度和良好的生物相容性，具有适合组织再生的多孔结构，可用于制备肛瘘修补塞。

2. 发明授权

US6101598A Methods for debugging a multiprocessor system 失效
标题翻译：调试多处理器系统的方法
公开(公告)号：US6101598A
公开(公告)日：2000-08-08
申请号：US970372
申请日：1997-11-14
申请人： Miroslav Dokic , Raghunath Rao , Zheng Luo , Jeffrey Niehaus , James Divine
发明人： Miroslav Dokic , Raghunath Rao , Zheng Luo , Jeffrey Niehaus , James Divine
IPC分类号： G06F11/36 , G06F9/44
CPC分类号： G06F11/3656
摘要： A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.
摘要翻译：一种操作多处理器设备的方法。在一个寄存器中接收一个字序列的第一个字。从第一个字确定目标处理器，并且目标处理器被中断。输入就绪位被置位，并且用目标处理器读取寄存器中的第一个字。序列中的多个单词遵循从第一个单词确定的第一个单词。一个字计数器被设置并且输入就绪位被目标处理器清除。目标处理器返回主代码执行。

3. 发明申请

US20140043875A1 OFF-LINE REGULATOR AND ASSOCIATED METHOD 有权
标题翻译：离线调节器及相关方法
公开(公告)号：US20140043875A1
公开(公告)日：2014-02-13
申请号：US13572564
申请日：2012-08-10
申请人： Michael Hsing , Eric Yang , Zheng Luo , Ken Yi , Yiqing Jin , Yuancheng Ren
发明人： Michael Hsing , Eric Yang , Zheng Luo , Ken Yi , Yiqing Jin , Yuancheng Ren
IPC分类号： H02M7/04
CPC分类号： H02M7/2176 , G05F1/56 , H02M2001/0045
摘要： The present invention discloses an off-line regulator. The off-line regulator comprises a rectification circuit configured to rectify an AC line voltage into a rectified line voltage; a pass device coupled between the rectified line voltage and a first capacitor, the pass device is configured to be turned ON or OFF according to a comparison signal indicating whether the rectified line voltage is over a threshold voltage. The first capacitor delivers an interim voltage into a converter which supplies power to a load. Wherein a second capacitor coupled across a driver which driving the pass device is charged by the first capacitor when the comparison signal is at a first state, and the driver is boosted when the comparison signal is at a second state.
摘要翻译：本发明公开了一种离线调节器。离线调节器包括：整流电路，被配置为将AC线电压整流为整流线电压; 耦合在整流线路电压和第一电容器之间的通过装置，根据指示整流线路电压是否超过阈值电压的比较信号，通过装置被配置为接通或关断。第一个电容器将中间电压提供给向负载供电的转换器。其中当比较信号处于第一状态时，驱动通过装置的驱动器耦合的第二电容器被第一电容器充电，并且当比较信号处于第二状态时驱动器被升压。

4. 发明申请

US20050094729A1 Software and hardware partitioning for multi-standard video compression and decompression 审中-公开
标题翻译：用于多标准视频压缩和解压缩的软件和硬件分区
公开(公告)号：US20050094729A1
公开(公告)日：2005-05-05
申请号：US10913574
申请日：2004-08-06
申请人： John Yuan , Steven Smith , Srikrishna Ramaswamy , Zheng Luo
发明人： John Yuan , Steven Smith , Srikrishna Ramaswamy , Zheng Luo
IPC分类号： H04N7/12 , H04N7/26 , H04N7/50
CPC分类号： H04N19/42 , H04N19/61
摘要： A system, method, and computer readable medium adapted to provide software and hardware partitioning for multi-standard video compression and decompression comprises a master-slave bus, a peer-to-peer bus, and an inter-processor communications bus, a prediction engine, a filter engine, and a transform engine, and a video encode control processor, and a video decode control processor adapted to utilize the master-slave bus to interact with the video hardware engines for control flow processing, the peer-to-peer bus for data flow processing, and the inter-processor communications bus for inter-processor communications, and a system data bus adapted to permit data exchange between system resources, the busses, the engines, and the processors.
摘要翻译：适于提供用于多标准视频压缩和解压缩的软件和硬件分区的系统，方法和计算机可读介质包括主 - 从总线，对等总线和处理器间通信总线，预测引擎，滤波器引擎和变换引擎，以及视频编码控制处理器，以及视频解码控制处理器，其适于利用主从总线与视频硬件引擎进行交互以进行控制流处理，对等总线用于数据流处理，以及用于处理器间通信的处理器间通信总线，以及适于允许系统资源，总线，引擎和处理器之间的数据交换的系统数据总线。

5. 发明授权

US06316991B1 Out-of-calibration circuits and methods and systems using the same 有权
标题翻译：不合标准的电路和使用该电路的方法和系统
公开(公告)号：US06316991B1
公开(公告)日：2001-11-13
申请号：US09537605
申请日：2000-03-29
申请人： Gabriel Patrick Muyshondt , Zheng Luo
发明人： Gabriel Patrick Muyshondt , Zheng Luo
IPC分类号： G05F110
CPC分类号： H03L7/06 , G01R19/16528 , G01R19/16595
摘要： A voltage out-of-calibration detector 200 includes a voltage divider operating between first and second voltage rails and having a plurality of taps 203 for generating first and second comparison voltages. A first set of switches 205 selectively couples at least one of the plurality of taps 203 to the input of a first voltage comparator 401a, first voltage comparator 401a comparing the first comparison voltage with an input voltage and outputing a signal when the input voltage exceeds the first comparison voltage. A second set of switches 206 selectively couples at least one of the plurality of taps 203 to an input of a second voltage comparator 401b, second voltage comparator 401b comparing the second comparison voltage with the input voltage and outputing a signal when the input voltage is below the second comparison voltage. Control logic 300 selectively activates the first and second sets of switches 205/206 in response to received control signals.
摘要翻译：电压校准外检测器200包括在第一和第二电压轨之间运行并具有多个用于产生第一和第二比较电压的抽头203的分压器。第一组开关205将多个抽头203中的至少一个选择性地耦合到第一电压比较器401a的输入，第一电压比较器401a将第一比较电压与输入电压进行比较，并且当输入电压超过第一比较电压。第二组开关206将多个抽头203中的至少一个选择性地耦合到第二电压比较器401b的输入，第二电压比较器401b将第二比较电压与输入电压进行比较，并且当输入电压低于时输出信号第二比较电压。响应于所接收的控制信号，控制逻辑300选择性地激活第一和第二组开关205/206。

6. 发明授权

US6145007A Interprocessor communication circuitry and methods 失效
标题翻译：处理器间通信电路和方法
公开(公告)号：US6145007A
公开(公告)日：2000-11-07
申请号：US969883
申请日：1997-11-14
申请人： Miroslav Dokic , Raghunath Rao , Jeffrey Niehaus , Zheng Luo , James Divine
发明人： Miroslav Dokic , Raghunath Rao , Jeffrey Niehaus , Zheng Luo , James Divine
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4022
摘要： A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a message is written into a second register with the first processor. The pending flag is set to a second selected logic state with the first processor and an interrupt to the second processor is generated. The message is read from the second register with the second processor when the pending flag is in the second logic state. The pending flag set to the first logic state with the second processor.
摘要翻译：一种在第一和第二处理器之间交换消息的方法。由第一处理器轮询第一寄存器中的未决标志，如果标志处于第一选择的逻辑状态，则将消息写入与第一处理器的第二寄存器。待处理标志被设置为具有第一处理器的第二选择的逻辑状态，并且产生到第二处理器的中断。当挂起标志处于第二逻辑状态时，从第二个寄存器读取该消息。待处理标志设置为与第二处理器的第一逻辑状态。

7. 发明授权

US08917076B2 Off-line regulator with pass device and associated method 有权
标题翻译：离线调节器带通过装置及相关方法
公开(公告)号：US08917076B2
公开(公告)日：2014-12-23
申请号：US13572564
申请日：2012-08-10
申请人： Michael R. Hsing , Eric Yang , Zheng Luo , Ken Yi , Yiqing Jin , Yuancheng Ren
发明人： Michael R. Hsing , Eric Yang , Zheng Luo , Ken Yi , Yiqing Jin , Yuancheng Ren
IPC分类号： G05F1/00 , H02M7/04
CPC分类号： H02M7/2176 , G05F1/56 , H02M2001/0045
摘要： An off-line regulator has a rectification circuit configured to rectify an AC line voltage into a rectified line voltage, a pass device coupled between the rectified line voltage and a first capacitor, and a converter. The pass device is configured to be turned ON or OFF according to a comparison signal indicating whether the rectified line voltage is over a threshold voltage. The first capacitor delivers an interim voltage into the converter which supplies power to a load. Wherein a second capacitor coupled across a driver which driving the pass device is charged by the first capacitor when the comparison signal is at a first state, and the driver is boosted when the comparison signal is at a second state.
摘要翻译：离线调节器具有整流电路，其被配置为将AC线电压整流为整流线电压，耦合在整流线电压和第一电容器之间的通过器件以及转换器。通过装置被配置为根据指示整流的线路电压是否超过阈值电压的比较信号而导通或关断。第一个电容器向转换器提供中间电压，为转换器供电。其中当比较信号处于第一状态时，驱动通过装置的驱动器耦合的第二电容器被第一电容器充电，并且当比较信号处于第二状态时驱动器被升压。

8. 发明申请

US20130176009A1 SMART LOW DROP-OUT VOLTAGE REGULATOR AND ASSOCIATED METHOD 审中-公开
标题翻译：智能低压降稳压器及相关方法
公开(公告)号：US20130176009A1
公开(公告)日：2013-07-11
申请号：US13347378
申请日：2012-01-10
申请人： Eric Yang , Zheng Luo
发明人： Eric Yang , Zheng Luo
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , H02M3/156 , H02M7/2176
摘要： The present disclosure discloses a low drop-out voltage regulator and an electronic device comprising the same. The present disclosure also discloses a method for converting a power supply voltage to a regulated output voltage. The low drop-out voltage regulator comprises a pass device controllable to convert a power supply voltage to a regulated output voltage; and a controller configured to receive an input signal and to provide a driving signal to the control terminal of the pass device based on the input signal, wherein when the input signal is within a predetermined range, the driving signal turns the pass device ON, and the power supply voltage charges the output voltage; and wherein when the input signal is without the predetermined range, the driving signal turns the pass device OFF, and the power supply voltage stops charging the output voltage.
摘要翻译：本公开公开了一种低压差稳压器和包括该低压降稳压器的电子设备。本公开还公开了一种用于将电源电压转换为稳定的输出电压的方法。低压差稳压器包括可控的将通电电压转换成稳压输出电压的通过装置; 以及控制器，被配置为基于所述输入信号接收输入信号并向所述通过装置的控制端提供驱动信号，其中当所述输入信号在预定范围内时，所述驱动信号使所述通过装置接通，以及电源电压对输出电压充电; 并且其中当所述输入信号没有所述预定范围时，所述驱动信号使所述通过装置关闭，并且所述电源电压停止对所述输出电压充电。

9. 发明授权

US06385704B1 Accessing shared memory using token bit held by default by a single processor 失效
标题翻译：使用单个处理器默认保存的令牌位访问共享内存
公开(公告)号：US06385704B1
公开(公告)日：2002-05-07
申请号：US08969884
申请日：1997-11-14
申请人： Raghunath Rao , Miroslav Dokic , Zheng Luo , Jeffrey Niehaus , James Divine
发明人： Raghunath Rao , Miroslav Dokic , Zheng Luo , Jeffrey Niehaus , James Divine
IPC分类号： G06F1200
CPC分类号： G10L19/16
摘要： A method of operating shared memory in a multiple processor system. A token is by default maintained with a first processor, the token enabling access to shared memory. A determination is made that a second processor requires access to shared memory. A determination is also made as to whether the first processor is accessing to the shared memory. The token is transferred the second processor if the first processor is not accessing the shared memory. The second processor accesses the shared memory with the token.
摘要翻译：一种在多处理器系统中操作共享存储器的方法。默认情况下，使用第一个处理器维护令牌，令牌允许访问共享内存。确定第二处理器需要访问共享存储器。还确定第一处理器是否正在访问共享存储器。如果第一个处理器没有访问共享存储器，令牌将传输第二个处理器。第二个处理器使用令牌访问共享内存。

10. 发明授权

US06253293B1 Methods for processing audio information in a multiple processor audio decoder 有权
标题翻译：用于处理多处理器音频解码器中的音频信息的方法
公开(公告)号：US06253293B1
公开(公告)日：2001-06-26
申请号：US09483290
申请日：2000-01-14
申请人： Raghunath Rao , Miroslav Dokic , Zheng Luo , Jeffrey Niehaus , James Divine
发明人： Raghunath Rao , Miroslav Dokic , Zheng Luo , Jeffrey Niehaus , James Divine
IPC分类号： G06F1200
CPC分类号： G10L19/16
摘要： A method of processing a stream of audio information received by a multiple processor audio decoder. Processing operations are performed by a first processor on the stream of audio information to produce at set of results. The first processor writes the set of results into a shared memory and a flag is set indicating that the results are ready. In response to the flag, a second processor reads the results from shared memory. When the results have been read from shared memory, the second processor sends a command to the first processor. The first processor then clears the flag.
摘要翻译：一种处理由多处理器音频解码器接收的音频信息流的方法。处理操作由音频信息流上的第一处理器执行以产生一组结果。第一个处理器将该组结果写入共享内存，并设置一个标志，表示结果已准备就绪。响应该标志，第二个处理器从共享存储器读取结果。当从共享存储器读取结果时，第二处理器向第一处理器发送命令。然后第一个处理器清除该标志。

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