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1. 发明申请

WO2011088378A1 SYSTEM AND METHOD TO CONTROL A DIRECTION OF A CURRENT APPLIED TO A MAGNETIC TUNNEL JUNCTION 审中-公开
标题翻译：用于控制应用于磁性隧道结的电流的方向的系统和方法
公开(公告)号：WO2011088378A1
公开(公告)日：2011-07-21
申请号：PCT/US2011/021380
申请日：2011-01-14
申请人： QUALCOMM Incorporated , KIM, Jung, Pill , RAO, Hari, M. , LEE, Kangho
发明人： KIM, Jung, Pill , RAO, Hari, M. , LEE, Kangho
IPC分类号： G11C11/16 , H01L43/08
CPC分类号： G11C11/1673 , H01L43/08
摘要： A system and method to control a direction of a current applied to a magnetic tunnel junction (139) is disclosed. In a particular embodiment, an apparatus comprises a magnetic tunnel junction (MTJ) storage element and a sense amplifier (102). The sense amplifier is coupled to a first path (114) and to a second path (116). The first path includes a first current direction selecting transistor (118) and the second path includes a second current direction selecting transistor (120). The first path is coupled to a bit line (140) of the MTJ storage element and the second path is coupled to a source line (142) of the MTJ storage element.
摘要翻译：公开了一种控制施加到磁性隧道结（139）的电流的方向的系统和方法。在特定实施例中，一种装置包括磁性隧道结（MTJ）存储元件和读出放大器（102）。读出放大器耦合到第一路径（114）和第二路径（116）。第一路径包括第一电流方向选择晶体管（118），并且第二路径包括第二电流方向选择晶体管（120）。第一路径耦合到MTJ存储元件的位线（140），并且第二路径耦合到MTJ存储元件的源极线（142）。

2. 发明申请

WO2012018918A2 GENERATING A NON-REVERSIBLE STATE AT A BITCELL HAVING A FIRST MAGNETIC TUNNEL JUNCTION AND A SECOND MAGNETIC TUNNEL JUNCTION 审中-公开
标题翻译：在具有第一磁性隧道接头和第二磁性隧道接头的位置处产生不可逆状态
公开(公告)号：WO2012018918A2
公开(公告)日：2012-02-09
申请号：PCT/US2011/046429
申请日：2011-08-03
申请人： QUALCOMM INCORPORATED , RAO, Hari, M. , KIM, Jung, Pill , KANG, Seung, H. , ZHU, Xiaochun , KIM, Tae, Hyun , LEE, Kangho , LI, Xia , HSU, Wah, Nam , HAO, Wuyang , SUH, Jungwon , YU, Nicholas, K. , NOWAK, Matthew, Michael , MILLENDORF, Steven, M. , ASHKENAZI, Asaf
发明人： RAO, Hari, M. , KIM, Jung, Pill , KANG, Seung, H. , ZHU, Xiaochun , KIM, Tae, Hyun , LEE, Kangho , LI, Xia , HSU, Wah, Nam , HAO, Wuyang , SUH, Jungwon , YU, Nicholas, K. , NOWAK, Matthew, Michael , MILLENDORF, Steven, M. , ASHKENAZI, Asaf
IPC分类号： G11C17/16
CPC分类号： G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
摘要： A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.
摘要翻译：在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。存储器件包括具有第一MTJ和第二MTJ的位单元以及被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个而在位单元处产生不可逆状态的编程电路。

3. 发明申请

WO2013016467A1 NON-VOLATILE MEMORY SAVING CELL INFORMATION IN A NON-VOLATILE MEMORY ARRAY 审中-公开
标题翻译：在非易失性存储器阵列中的非易失性存储器保存单元信息
公开(公告)号：WO2013016467A1
公开(公告)日：2013-01-31
申请号：PCT/US2012/048208
申请日：2012-07-25
申请人： QUALCOMM INCORPORATED , KIM, Jung, Pill , KIM, Taehyun , RAO, Hari, M.
发明人： KIM, Jung, Pill , KIM, Taehyun , RAO, Hari, M.
IPC分类号： G11C11/16 , G11C29/00
CPC分类号： G11C11/16 , G11C29/846 , G11C2029/4402
摘要： Systems and methods for saving repair cell address information in a non-volatile magnetoresistive random access memory (MRAM) having an array (510) of MRAM cells are disclosed. A memory access circuit (535) is coupled to the MRAM, and is configured to store failed cell address information (525) in the MRAM.
摘要翻译：公开了在具有MRAM单元的阵列（510）的非易失性磁阻随机存取存储器（MRAM）中保存修复单元地址信息的系统和方法。存储器访问电路（535）耦合到MRAM，并且被配置为在MRAM中存储故障小区地址信息（525）。

4. 发明申请

WO2011119938A1 REFERENCE CELL WRITE OPERATIONS IN A MEMORY 审中-公开
标题翻译：存储器中的参考单元写操作
公开(公告)号：WO2011119938A1
公开(公告)日：2011-09-29
申请号：PCT/US2011/029967
申请日：2011-03-25
申请人： QUALCOMM INCORPORATED , KIM, Jung, Pill , RAO, Hari, M. , LI, Xia
发明人： KIM, Jung, Pill , RAO, Hari, M. , LI, Xia
IPC分类号： G11C8/10 , G11C11/16 , G11C13/00
CPC分类号： G11C13/004 , G11C8/10 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0023 , G11C13/0026 , G11C2013/0054
摘要： A method of selecting a reference circuit for a write operation is disclosed. The method comprises selecting a reference circuit for a write operation based on an output of a row decode circuit and a column decode circuit. The reference circuit is programmed concurrently with a write operation of at least one of a plurality of memory cells in a memory array without requiring an external reference circuit write command.
摘要翻译：公开了一种选择用于写入操作的参考电路的方法。该方法包括基于行解码电路和列解码电路的输出来选择用于写入操作的参考电路。参考电路与存储器阵列中的多个存储单元中的至少一个的写入操作同时编程，而不需要外部参考电路写入命令。

5. 发明申请

WO2011100244A1 SYSTEM AND METHOD TO SELECT A REFERENCE CELL 审中-公开
标题翻译：选择参考电池的系统和方法
公开(公告)号：WO2011100244A1
公开(公告)日：2011-08-18
申请号：PCT/US2011/024050
申请日：2011-02-08
申请人： QUALCOMM Incorporated , KIM, Jung, Pill , KIM, Tae, Hyun , RAO, Hari, M.
发明人： KIM, Jung, Pill , KIM, Tae, Hyun , RAO, Hari, M.
IPC分类号： G11C29/00
CPC分类号： G11C7/14 , G11C8/12 , G11C11/1673 , G11C29/808
摘要： A system and method to select a reference cell is disclosed. In a particular embodiment, a method is disclosed that includes receiving an address (118) corresponding to a bit cell (110) within a first bank (104) of a memory. The method also includes accessing a second reference cell (116) of a second bank (106) of the memory in response to a first reference cell (114) in the first bank (104) being indicated as bypassed.
摘要翻译：公开了一种选择参考单元的系统和方法。在特定实施例中，公开了一种方法，其包括接收对应于存储器的第一存储体（104）内的位单元（110）的地址（118）。该方法还包括响应于被指示为旁路的第一组（104）中的第一参考单元（114），访问存储器的第二存储体（106）的第二参考单元（116）。

6. 发明申请

WO2012033884A1 SYSTEM AND METHOD FOR SHARED SENSING MRAM 审中-公开
标题翻译：用于共享感测MRAM的系统和方法
公开(公告)号：WO2012033884A1
公开(公告)日：2012-03-15
申请号：PCT/US2011/050779
申请日：2011-09-08
申请人： QUALCOMM INCORPORATED , KIM, Jung, Pill , KIM, Tae, Hyun
发明人： KIM, Jung, Pill , KIM, Tae, Hyun
IPC分类号： G11C11/16
CPC分类号： G11C11/1693 , G11C11/1673
摘要： Resistance memory cells of MRAM arrays are designated as reference cells and programmed to binary 0 and binary 1 states, reference cells from one MRAM array at binary 0 and at binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of another MRAM array, reference cells from the other MRAM array at binary 0 and binary 1 are concurrently accessed to obtain a reference voltage to read resistance memory cells of the one MRAM array.
摘要翻译：将MRAM阵列的电阻存储单元指定为参考单元，并编程为二进制0和二进制1状态，同时访问来自二进制0和二进制1的一个MRAM阵列的参考单元以获得参考电压以读取另一MRAM的电阻存储单元数组，二进制0和二进制1的其他MRAM阵列的参考单元被同时访问，以获得参考电压以读取一个MRAM阵列的电阻存储单元。

7. 发明申请

WO2005050655A1 LATCH SCHEME WITH INVALID COMMAND DETECTOR 审中-公开
标题翻译：具有无效命令检测器的锁定方案
公开(公告)号：WO2005050655A1
公开(公告)日：2005-06-02
申请号：PCT/EP2004/012871
申请日：2004-11-12
申请人： INFINEON TECHNOLOGIES AG , CAMACHO, Stephen, Michael , HAN, Jonghee , KIM, Jung, Pill
发明人： CAMACHO, Stephen, Michael , HAN, Jonghee , KIM, Jung, Pill
IPC分类号： G11C7/10
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/1087 , G11C8/06 , G11C11/4082 , G11C11/4093
摘要： Methods and circuits for reducing unnecessary changes to outputs of latch circuits are provided. Unnecessary changes to outputs of latch circuits may be reduced by preventing the outputs of the latch circuits from changing when an invalid command is detected. For some embodiments, an invalid command detector is provided that generates an invalid command signal used to inhibit latch circuits, in response to detecting an invalid command.
摘要翻译：提供了用于减少对锁存电路的输出的不必要的改变的方法和电路。当检测到无效命令时，可以通过防止锁存电路的输出改变来减少对锁存电路的输出的不必要的改变。对于一些实施例，提供无效命令检测器，其响应于检测到无效命令而产生用于禁止锁存电路的无效命令信号。

8. 发明申请

WO2005050654A2 BACK-BIAS VOLTAGE GENERATOR WITH TEMPERATURE CONTROL 审中-公开
标题翻译：具有温度控制的后置偏压发电机
公开(公告)号：WO2005050654A2
公开(公告)日：2005-06-02
申请号：PCT/EP2004/013133
申请日：2004-11-18
申请人： INFINEON TECHNOLOGIES AG , KIM, Jung, Pill
发明人： KIM, Jung, Pill
IPC分类号： G11C5/14
CPC分类号： G11C7/04 , G11C5/14 , G11C11/4074
摘要： Methods and apparatus for varying one or more internally generated voltages of a memory device based on the temperature of the memory device are provided. The device temperature may be measured directly, for example, via an on-chip temperature sensor, or may be supplied as bits in a mode register containing temperature information.
摘要翻译：提供了用于基于存储器件的温度改变存储器件的一个或多个内部产生的电压的方法和装置。器件温度可以直接例如通过片上温度传感器测量，或者可以作为包含温度信息的模式寄存器中的位来提供。

9. 发明申请

WO2006042643A1 DQS FOR DATA FROM A MEMORY ARRAY 审中-公开
标题翻译：来自存储阵列的数据DQS
公开(公告)号：WO2006042643A1
公开(公告)日：2006-04-27
申请号：PCT/EP2005/010787
申请日：2005-10-06
申请人： INFINEON TECHNOLOGIES AG , KIM, Jung, Pill , MINZONI, Alessandro
发明人： KIM, Jung, Pill , MINZONI, Alessandro
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/227
摘要： A memory comprises a first circuit, a second circuit, and a latch. The first circuit is configured to provide a first signal indicating an earliest time valid data is available from a memory array in response to a read command. The second circuit is configured to provide a second signal indicating a latest time valid data is available from the memory array in response to the read command. The latch is configured to be connected to a data line coupled to the memory array in response to the first signal and disconnected from the data line in response to the second signal to latch data read from the memory array.
摘要翻译：存储器包括第一电路，第二电路和锁存器。第一电路被配置为响应于读取命令提供指示最早时间有效数据从存储器阵列可用的第一信号。第二电路被配置为响应于读取命令提供指示最新时间有效数据从存储器阵列可用的第二信号。锁存器被配置为响应于第一信号而连接到耦合到存储器阵列的数据线，并响应于第二信号与数据线断开以锁存从存储器阵列读取的数据。

10. 发明申请

WO2005031750A1 TEMPERATURE SENSOR SCHEME 审中-公开
标题翻译：温度传感器方案
公开(公告)号：WO2005031750A1
公开(公告)日：2005-04-07
申请号：PCT/EP2004/010579
申请日：2004-09-21
申请人： INFINEON TECHNOLOGIES AG , KIM, Jung, Pill
发明人： KIM, Jung, Pill
IPC分类号： G11C11/406
CPC分类号： G11C11/40626 , G01K3/005 , G01K7/015 , G01K15/00 , G11C11/406
摘要： The present invention is a random access memory device including a temperature sensing circuit, and method of using the same. The temperature sensing circuit includes a first and a second comparator. Each comparator is configured to receive a sense voltage that is indicative of a sensed temperature. A first temperature reference circuit having a plurality of first reference voltages is coupled to the first comparator. The plurality of first reference voltages are alternately compared with the sense voltage. A second temperature reference circuit having a plurality of second reference voltages is coupled to the second comparator. The plurality of second reference voltages are alternately compared with the sense voltage. A first trimmer is coupled to the first temperature reference circuit. A second trimmer coupled to the second temperature reference circuit. The first and second trimmers are independently adjustable to adjust the plurality of first and second reference voltages.
摘要翻译：本发明是一种包括温度检测电路的随机存取存储器件及其使用方法。温度检测电路包括第一和第二比较器。每个比较器被配置为接收指示感测温度的感测电压。具有多个第一参考电压的第一温度参考电路被耦合到第一比较器。多个第一参考电压与感测电压交替地进行比较。具有多个第二参考电压的第二温度参考电路被耦合到第二比较器。将多个第二参考电压与感测电压交替地进行比较。第一微调器耦合到第一温度参考电路。耦合到第二温度参考电路的第二微调器。第一和第二微调器可独立调节以调节多个第一和第二参考电压。

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