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1. 发明申请

US20160378166A1 POWER SAVING DURING A CONNECTION DETECTION 审中-公开
标题翻译：在连接检测期间节电
公开(公告)号：US20160378166A1
公开(公告)日：2016-12-29
申请号：US15260355
申请日：2016-09-09
申请人： QUALCOMM Incorporated
发明人： Cheng Zhong , Nam Van Dang , Hung Quoc Vuong , Xiaohua Kong
IPC分类号： G06F1/32 , G06F11/30 , G06F11/22 , G06F13/40
摘要： An electronic device includes a receiver sense circuit configured to generate a detection signal responsive to detecting a connection to a sink device via a connector. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to enable a direct current (DC) voltage source based on the detection signal received from the receiver sense circuit.
摘要翻译：电子设备包括接收机感测电路，其被配置为响应于经由连接器检测到与设备的连接而产生检测信号。电子设备还包括耦合到热插拔检测（HPD）接口的控制器。控制器被配置为基于从接收机感测电路接收的检测信号来启用直流（DC）电压源。

2. 发明授权

US09485084B2 Linearity of phase interpolators by combining current coding and size coding 有权
标题翻译：通过组合当前编码和大小编码来实现相位内插器的线性度
公开(公告)号：US09485084B2
公开(公告)日：2016-11-01
申请号：US14300127
申请日：2014-06-09
申请人： Qualcomm Incorporated
发明人： Li Sun , Zhi Zhu , Xiaohua Kong , Kenneth Luis Arcudia , Zhiqin Chen
IPC分类号： H04L7/033 , H03L7/099 , H03K5/135 , H03K5/00
CPC分类号： H04L7/0331 , H03K5/135 , H03K2005/00065 , H03L7/099
摘要： A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.
摘要翻译：一种相位插值器，包括：包括第一多个分支和多个尾电流源的第一部分，每个分支包括差分对晶体管，所述差分对晶体管的源极端子连接以形成源节点，其中每个尾部电流源耦合到源节点之一，并且其中所述差分对晶体管和相应的尾电流源以当前编码方案配置; 第二部分包括第二多个分支和耦合到第二多个分支的固定电流源，第二多个分支的每个分支包括第二多个差分对晶体管和多个开关，其以尺寸编码方案 ; 其中所述第一部分和所述第二部分彼此耦合并耦合到一对负载电阻器。

3. 发明授权

US09459650B2 Clock pulse generator for multi-phase signaling 有权
标题翻译：时钟脉冲发生器用于多相信号
公开(公告)号：US09459650B2
公开(公告)日：2016-10-04
申请号：US14496129
申请日：2014-09-25
申请人： QUALCOMM Incorporated
发明人： Xiaohua Kong , Cheng Zhong , Swarna Latha Navubothu
IPC分类号： G06F1/04 , H03K3/00 , H03K5/01 , G11C11/4076 , H04L25/02 , H04L25/14 , H03K5/00
CPC分类号： G06F1/04 , G11C11/4076 , H03K5/01 , H03K2005/00013 , H04L25/0292 , H04L25/14
摘要： A clock generator is provided that is immune to skew between bits in digital words generated by a multi-phase receiver.
摘要翻译：提供了一种时钟发生器，其免受由多相接收器产生的数字字中的位之间的偏斜。

4. 发明授权

US09246477B2 Systems and methods for common mode level shifting 有权
标题翻译：用于共模转换的系统和方法
公开(公告)号：US09246477B2
公开(公告)日：2016-01-26
申请号：US14228049
申请日：2014-03-27
申请人： QUALCOMM Incorporated
发明人： Miao Li , Xiaohua Kong , Zhi Zhu , Jie Xu
IPC分类号： H03K19/0175 , H03K3/356
CPC分类号： H03K3/35613 , H03F3/45475 , H03F2200/291 , H03F2203/45081 , H03F2203/45084
摘要： A common mode voltage level shifting circuit including: input nodes configured to receive a differential signal with a first common mode voltage, a pair of shunt capacitors coupled between the input nodes and a corresponding pair of output nodes, a threshold voltage circuit, including the output nodes, coupled to the differential signal though the shunt capacitors, the threshold voltage circuit configured to provide a second common mode voltage for the differential signal at the output nodes, and current sources that are controlled according to a level of the first common mode voltage, the current sources coupled to the output nodes to effect the second common mode voltage.
摘要翻译：一种共模电压电平移位电路，包括：被配置为接收具有第一共模电压的差分信号的输入节点，耦合在输入节点之间的一对并联电容器和相应的一对输出节点，包括输出端的阈值电压电路节点，其通过并联电容器耦合到差分信号，阈值电压电路被配置为为输出节点处的差分信号提供第二共模电压，以及根据第一共模电压的电平来控制的电流源，电流源耦合到输出节点以实现第二共模电压。

5. 发明授权

US09209789B1 Apparatus to convert electrical signals from small-signal format to rail-to-rail format 有权
标题翻译：将电信号从小信号格式转换为轨到轨格式的装置
公开(公告)号：US09209789B1
公开(公告)日：2015-12-08
申请号：US14459168
申请日：2014-08-13
申请人： QUALCOMM Incorporated
发明人： Miao Li , Xiaohua Kong , Dong Ren
IPC分类号： H03L5/00 , H03K5/02 , H03K19/0175
CPC分类号： H03F3/505 , H03F1/0272 , H03F3/45183 , H03F3/4565 , H03F3/45708 , H03F2200/453 , H03F2200/78 , H03F2203/45292 , H03F2203/45416 , H03F2203/45418 , H03F2203/45424 , H03F2203/45594 , H03F2203/45604 , H03F2203/45664 , H03F2203/45702 , H04L25/0276
摘要： Techniques for converting a signal from a small-signal format into a rail-to-rail format are described herein. In one embodiment, a receiver comprises a voltage-level shifter configured to shift a common-mode voltage of a differential signal to obtain a level-shifted differential signal, an amplifier configured to amplify the level-shifted differential signal into an amplified differential signal, and a driver stage configured to convert the amplified differential signal into a rail-to-rail signal. The receiver also comprises a common-mode feedback circuit configured to generate a feedback voltage that is proportional to an output common-mode voltage of the amplifier, and to generate a bias voltage for input to the amplifier based on a difference between the feedback voltage and a reference voltage, wherein the output common-mode voltage of the amplifier depends on the bias voltage.
摘要翻译：这里描述了用于将信号从小信号格式转换为轨到轨格式的技术。在一个实施例中，接收机包括：电压电平移位器，被配置为移位差分信号的共模电压以获得电平移位的差分信号;放大器，被配置为将电平移位的差分信号放大为放大的差分信号，以及驱动器级，被配置为将放大的差分信号转换成轨到轨信号。接收机还包括共模反馈电路，其被配置为产生与放大器的输出共模电压成比例的反馈电压，并且基于反馈电压和反馈电压之间的差产生用于输入到放大器的偏置电压参考电压，其中放大器的输出共模电压取决于偏置电压。

6. 发明授权

US09195254B2 Method and apparatus for multi-level de-emphasis 有权
标题翻译：多级去加重的方法和装置
公开(公告)号：US09195254B2
公开(公告)日：2015-11-24
申请号：US13725961
申请日：2012-12-21
申请人： QUALCOMM Incorporated
发明人： Miao Li , Madjid Hafizi , Xiaohua Kong
IPC分类号： H03K3/00 , G05F3/26 , H04L25/03
CPC分类号： G05F3/262 , H04L25/03847
摘要： A distribution current is split into a first control current, a second control current, and a third control current, in an apportionment according to a distribution command. A first control voltage is generated in response to the third control current. A second control voltage is generated as indication of the first control current, and a third control voltage is generated as indication of the second control current. Optionally, de-emphasis contribution of a first driver, a second driver and a third driver to an output is controlled based, at least in part, on the first control voltage, the second control voltage and the third control voltage, respectively.
摘要翻译：根据分配命令，分配电流被分成第一控制电流，第二控制电流和第三控制电流。响应于第三控制电流产生第一控制电压。产生第二控制电压作为第一控制电流的指示，并且产生第三控制电压作为第二控制电流的指示。可选地，至少部分地基于第一控制电压，第二控制电压和第三控制电压来控制第一驱动器，第二驱动器和第三驱动器对输出的去加重贡献。

7. 发明申请

US20150261249A1 CLOCK PULSE GENERATOR FOR MULTI-PHASE SIGNALING 有权
标题翻译：用于多相信号的时钟脉冲发生器
公开(公告)号：US20150261249A1
公开(公告)日：2015-09-17
申请号：US14496129
申请日：2014-09-25
申请人： QUALCOMM Incorporated
发明人： Xiaohua Kong , Cheng Zhong , Swarna Latha Navubothu
IPC分类号： G06F1/04 , G11C11/4076 , H03K5/01
CPC分类号： G06F1/04 , G11C11/4076 , H03K5/01 , H03K2005/00013 , H04L25/0292 , H04L25/14
摘要： A clock generator is provided that is immune to skew between bits in digital words generated by a multi-phase receiver.
摘要翻译：提供了一种时钟发生器，其免受由多相接收机产生的数字字中的位之间的偏斜。

8. 发明申请

US20150008967A1 APPARATUS AND METHOD FOR RECOVERING BURST-MODE PULSE WIDTH MODULATION (PWM) AND NON-RETURN-TO-ZERO (NRZ) DATA 有权
标题翻译：用于恢复脉冲模式脉冲宽度调制（PWM）和非归零（NRZ）数据的装置和方法
公开(公告)号：US20150008967A1
公开(公告)日：2015-01-08
申请号：US14490952
申请日：2014-09-19
申请人： QUALCOMM Incorporated
发明人： Zhi Zhu , Xiaohua Kong , Nam Van Dang
IPC分类号： H03L7/08
CPC分类号： H03L7/0802 , H03L7/0805 , H03L7/0807 , H03L7/0995 , H04L7/0276 , H04L7/0338
摘要： A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.
摘要翻译：门控压控振荡器具有四个相同结构的延迟单元，每个延迟单元通过连接到其他延迟单元的相同数量的输入端而具有相同的输出负载。可选地，四相采样时钟从延迟单元输出中选择并在四相采样器处采样输入信号。可选地，边沿检测器将门控压控振荡器的相位同步到NRZ位。可选地，可变采样率选择来自延迟单元的不同相位以选择以较低速率对NRZ位进行采样。可选地，脉冲宽度调制（PWM）模式将采样时钟的相位同步到采样PWM符号并恢复编码比特。

9. 发明申请

US20140256276A1 UNIFIED FRONT-END RECEIVER INTERFACE FOR ACCOMMODATING INCOMING SIGNALS VIA AC-COUPLING OR DC-COUPLING 有权
标题翻译：用于通过交流耦合或直流耦合接收信号的统一的前端接收器接口
公开(公告)号：US20140256276A1
公开(公告)日：2014-09-11
申请号：US13784821
申请日：2013-03-05
申请人： QUALCOMM INCORPORATED
发明人： Miao Li , Xiaohua Kong , Jingcheng Zhuang , Wei Wang
IPC分类号： H04B1/18
CPC分类号： H04B3/50 , H04B3/30
摘要： Techniques for accommodating an incoming signal at a front-end receiver via AC-coupling or DC-coupling are described herein. In one aspect, a front-end receiver comprises a differential input with a first data line and a second data line for receiving an incoming signal. The front-end receiver also comprises an AC-coupled switch coupled to the differential input, wherein the AC-coupled switch is configured to both perform high-pass filtering on the incoming signal and offset the filtered incoming signal with a DC-offset voltage if an AC-coupling mode of the receiver is enabled. The front-end receiver further comprises a DC-coupled switch coupled to the differential input, wherein the DC-coupled switch is configured to shift a common-mode voltage of the incoming signal if a DC-coupling mode of the receiver is enabled.
摘要翻译：这里描述了用于通过AC耦合或DC耦合在前端接收器处容纳输入信号的技术。一方面，前端接收机包括具有第一数据线的差分输入和用于接收输入信号的第二数据线。前端接收器还包括耦合到差分输入的AC耦合开关，其中AC耦合开关被配置为对输入信号执行高通滤波，并且通过DC偏移电压偏移滤波的输入信号，如果接收器的AC耦合模式被使能。前端接收器还包括耦合到差分输入的DC耦合开关，其中如果接收器的DC耦合模式被使能，则DC耦合开关被配置为移位输入信号的共模电压。

10. 发明授权

US08811458B2 Digitally controlled jitter injection for built in self-testing (BIST) 有权
标题翻译：用于内置自检（BIST）的数字控制抖动注入
公开(公告)号：US08811458B2
公开(公告)日：2014-08-19
申请号：US13645260
申请日：2012-10-04
申请人： QUALCOMM Incorporated
发明人： Xiaohua Kong , Zhi Zhu , Vannam Dang
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： G01R31/31709 , H04B17/104 , H04B17/11 , H04B17/16 , H04B17/19 , H04L1/205
摘要： A digitally controlled jitter injection apparatus for built in self-testing includes a transceiver circuit having a transmitter circuit and a receiver circuit. The digitally controlled jitter injection apparatus also includes a generator that generates a composite jitter including multi-tone jitter components. The digitally controlled jitter injection apparatus also includes a processor operable to digitally inject the composite jitter into a receiver circuit and/or a transmitter circuit of the transceiver circuit.
摘要翻译：用于内置自检的数字控制抖动注入装置包括具有发射器电路和接收器电路的收发器电路。数字控制的抖动注入装置还包括产生包括多音调抖动分量的复合抖动的发生器。数字控制的抖动注入装置还包括可操作以将复合抖动数字地注入收发器电路的接收机电路和/或发射机电路的处理器。

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