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1. 发明授权

US08972818B2 Algorithm for optimal usage of external memory tuning sequence 有权
标题翻译：外部存储器调优序列的最优使用算法
公开(公告)号：US08972818B2
公开(公告)日：2015-03-03
申请号：US13672693
申请日：2012-11-08
申请人： QUALCOMM Incorporated
发明人： Nir Strauss , Racheli Angel Manor
IPC分类号： H03M13/00
CPC分类号： G06F13/102 , G06F13/1689
摘要： A method, an apparatus, and a computer program product for optimally tuning a memory card in a host device are provided. The apparatus determines at least one tuning parameter associated with the memory card, initiates a reading operation with the memory card, and sends a tuning command to the memory card based on the at least one tuning parameter. The at least one tuning parameter includes a temperature of the memory card, a time elapsed since a last tuning sequence was performed, a number of data blocks sent from the memory card to the host device, and/or a number of transactions between the memory card and the host device. The apparatus also reads data from the memory card, detects a cyclic redundancy check (CRC) error associated with the read data, and sends the tuning command to the memory card upon detecting the CRC error.
摘要翻译：提供了一种用于在主机设备中优化存储卡的方法，装置和计算机程序产品。设备确定与存储卡相关联的至少一个调谐参数，启动与存储卡的读取操作，并且基于至少一个调谐参数向存储卡发送调谐命令。所述至少一个调谐参数包括存储卡的温度，从执行最后一个调整序列起经过的时间，从存储卡发送到主机设备的多个数据块，以及/或存储器之间的事务数卡和主机设备。该装置还从存储卡读取数据，检测与读取数据相关联的循环冗余校验（CRC）错误，并且在检测到CRC错误时将调谐命令发送到存储卡。

2. 发明申请

US20190155781A1 TRANSFER OF MASTER DUTIES TO A SLAVE ON A COMMUNICATION BUS 审中-公开
公开(公告)号：US20190155781A1
公开(公告)日：2019-05-23
申请号：US15819641
申请日：2017-11-21
申请人： QUALCOMM Incorporated
发明人： Lior Amarilio , Yuval Corey Hershko , Nir Strauss
IPC分类号： G06F13/42 , G06F13/364 , G06F15/78
CPC分类号： G06F13/4291 , G06F1/3287 , G06F13/362 , G06F13/364 , G06F15/7807
摘要： Systems and methods to transfer master duties to a slave on a communication bus are disclosed. A master of a communication bus determines that one or more slaves are capable of serving as a sub-master, including providing a clock signal and owning control information bits. Once that determination is made, the master may determine that processing within the master is not required for a particular activity on the bus. The master then alerts one such capable slave to prepare to assume sub-master duties. Once the slave confirms that the slave is ready to assume the sub-master duties, the master may transmit a handover frame on the bus, and the slave begins acting as a sub-master. The master may then enter a low-power state, which may promote power savings, reduce heat generation, and provide other advantages.

3. 发明申请

US20180196776A1 DATA BUS ACTIVATION IN AN ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20180196776A1
公开(公告)日：2018-07-12
申请号：US15402519
申请日：2017-01-10
申请人： QUALCOMM Incorporated
发明人： Yuval Corey Hershko , Lior Amarilio , Nir Strauss
IPC分类号： G06F13/42
CPC分类号： G06F13/4291
摘要： Data bus activation in an electronic device is provided. In one aspect, a host circuit determines a cumulative potential representing a cumulative fractional bus activation vote on a data line(s) in the data bus. The host circuit activates the data bus when the cumulative potential is greater than a configurable bus activation threshold. In another aspect, a device circuit(s) determines a selected signal strength threshold that is less than determined signal strength of an incoming signal. Accordingly, the device circuit(s) asserts a fractional potential corresponding to the selected signal strength threshold on the data line(s) as a fractional bus activation vote in the cumulative fractional bus activation vote. By activating the data bus based on the cumulative fractional bus activation vote, the host circuit can support timely data bus activation while preventing the data bus from being falsely activated, thus improving robustness of data bus activation in the electronic device.

4. 发明申请

US20140254446A1 WIRELESS PERSONAL AREA NETWORK DEVICE 有权
标题翻译：无线个人网络设备
公开(公告)号：US20140254446A1
公开(公告)日：2014-09-11
申请号：US14282417
申请日：2014-05-20
申请人： QUALCOMM Incorporated
发明人： Gilad Bornstein , Baruch Eruchimovitch , Nir Strauss
IPC分类号： H04W52/02
CPC分类号： H04W52/0251 , H04W52/0206 , H04W52/0212 , H04W84/18 , Y02D70/144 , Y02D70/162
摘要： Systems and methods for saving power by a personal area network (PAN) coordinator and a device are described herein. A PAN coordinator is provided to form a wireless PAN with one or more of the devices. Further, the PAN coordinator and the devices enter sleep states to save power. The wireless PAN is available when the PAN coordinator enters an active state.
摘要翻译：本文描述了由个人区域网（PAN）协调器和设备节省功率的系统和方法。提供PAN协调器以形成具有一个或多个设备的无线PAN。此外，PAN协调器和设备进入睡眠状态以节省电力。当PAN协调器进入活动状态时，无线PAN可用。

5. 发明申请

US20140101511A1 Algorithm for Optimal Usage of External Memory Tuning Sequence 有权
标题翻译：外部存储器调优序列的最佳使用算法
公开(公告)号：US20140101511A1
公开(公告)日：2014-04-10
申请号：US13672693
申请日：2012-11-08
申请人： QUALCOMM INCORPORATED
发明人： Nir Strauss , Racheli Angel Manor
IPC分类号： G06F3/00 , G06F11/10 , H03M13/00
CPC分类号： G06F13/102 , G06F13/1689
摘要： A method, an apparatus, and a computer program product for optimally tuning a memory card in a host device are provided. The apparatus determines at least one tuning parameter associated with the memory card, initiates a reading operation with the memory card, and sends a tuning command to the memory card based on the at least one tuning parameter. The at least one tuning parameter includes a temperature of the memory card, a time elapsed since a last tuning sequence was performed, a number of data blocks sent from the memory card to the host device, and/or a number of transactions between the memory card and the host device. The apparatus also reads data from the memory card, detects a cyclic redundancy check (CRC) error associated with the read data, and sends the tuning command to the memory card upon detecting the CRC error.
摘要翻译：提供了一种用于在主机设备中优化存储卡的方法，装置和计算机程序产品。设备确定与存储卡相关联的至少一个调谐参数，启动与存储卡的读取操作，并且基于至少一个调谐参数向存储卡发送调谐命令。所述至少一个调谐参数包括存储卡的温度，从执行最后一个调整序列起经过的时间，从存储卡发送到主机设备的多个数据块，和/或存储器之间的事务数卡和主机设备。该装置还从存储卡读取数据，检测与读取数据相关联的循环冗余校验（CRC）错误，并且在检测到CRC错误时将调谐命令发送到存储卡。

6. 发明授权

US10482056B2 Transfer of master duties to a slave on a communication bus 有权
公开(公告)号：US10482056B2
公开(公告)日：2019-11-19
申请号：US15819641
申请日：2017-11-21
申请人： QUALCOMM Incorporated
发明人： Lior Amarilio , Yuval Corey Hershko , Nir Strauss
IPC分类号： G06F13/42 , G06F1/3287 , G06F15/78 , G06F13/364
摘要： Systems and methods to transfer master duties to a slave on a communication bus are disclosed. A master of a communication bus determines that one or more slaves are capable of serving as a sub-master, including providing a clock signal and owning control information bits. Once that determination is made, the master may determine that processing within the master is not required for a particular activity on the bus. The master then alerts one such capable slave to prepare to assume sub-master duties. Once the slave confirms that the slave is ready to assume the sub-master duties, the master may transmit a handover frame on the bus, and the slave begins acting as a sub-master. The master may then enter a low-power state, which may promote power savings, reduce heat generation, and provide other advantages.

7. 发明授权

US10248613B2 Data bus activation in an electronic device 有权
公开(公告)号：US10248613B2
公开(公告)日：2019-04-02
申请号：US15402519
申请日：2017-01-10
申请人： QUALCOMM Incorporated
发明人： Yuval Corey Hershko , Lior Amarilio , Nir Strauss
IPC分类号： G06F13/20 , G06F13/42
摘要： Data bus activation in an electronic device is provided. In one aspect, a host circuit determines a cumulative potential representing a cumulative fractional bus activation vote on a data line(s) in the data bus. The host circuit activates the data bus when the cumulative potential is greater than a configurable bus activation threshold. In another aspect, a device circuit(s) determines a selected signal strength threshold that is less than determined signal strength of an incoming signal. Accordingly, the device circuit(s) asserts a fractional potential corresponding to the selected signal strength threshold on the data line(s) as a fractional bus activation vote in the cumulative fractional bus activation vote. By activating the data bus based on the cumulative fractional bus activation vote, the host circuit can support timely data bus activation while preventing the data bus from being falsely activated, thus improving robustness of data bus activation in the electronic device.

8. 发明授权

US09629091B2 Wireless personal area network device 有权
公开(公告)号：US09629091B2
公开(公告)日：2017-04-18
申请号：US14282417
申请日：2014-05-20
申请人： QUALCOMM Incorporated
发明人： Gilad Bornstein , Baruch Eruchimovitch , Nir Strauss
IPC分类号： H04W52/02 , H04W84/18
CPC分类号： H04W52/0251 , H04W52/0206 , H04W52/0212 , H04W84/18 , Y02D70/144 , Y02D70/162
摘要： Systems and methods for saving power by a personal area network (PAN) coordinator and a device are described herein. A PAN coordinator is provided to form a wireless PAN with one or more of the devices. Further, the PAN coordinator and the devices enter sleep states to save power. The wireless PAN is available when the PAN coordinator enters an active state.

9. 发明授权

US09519428B2 Dynamically improving performance of a host memory controller and a memory device 有权
标题翻译：动态提高主机内存控制器和存储设备的性能
公开(公告)号：US09519428B2
公开(公告)日：2016-12-13
申请号：US13628006
申请日：2012-09-26
申请人： QUALCOMM Incorporated
发明人： Nir Strauss , David Teb , Racheli Angel Manor
IPC分类号： G06F12/00 , G06F3/06
CPC分类号： G06F3/061 , G06F3/0634 , G06F3/064 , G06F3/0659 , G06F3/0673
摘要： Methods, apparatuses, systems, and computer-readable media for dynamically improving performance of a host memory controller and a hosted memory device are presented. According to one or more aspects, a memory controller may establish a data connection with a memory device. The memory controller may perform a first write operation of a plurality of write operations to the memory device using a first block size. Subsequently, the memory controller may perform a second write operation of the plurality of write operations to the memory device using a second block size different from the first block size. The memory controller then may determine an optimal value for a block size parameter based at least in part on the plurality of write operations. Thereafter, the memory controller may use the optimal value for the block size parameter in performing one or more regular tasks involving the memory device.
摘要翻译：提出了用于动态地提高主机存储器控制器和托管存储器设备的性能的方法，装置，系统和计算机可读介质。根据一个或多个方面，存储器控制器可建立与存储器件的数据连接。存储器控制器可以使用第一块大小来对存储器件执行多次写入操作的第一写入操作。随后，存储器控制器可以使用与第一块大小不同的第二块大小来对存储器件执行多次写入操作的第二写入操作。存储器控制器然后可以至少部分地基于多个写入操作来确定块大小参数的最佳值。此后，存储器控制器可以在执行涉及存储器件的一个或多个规则任务时使用块大小参数的最佳值。

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