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1. 发明申请

WO2007115330A2 IFFT PROCESSING IN WIRELESS COMMUNICATIONS 审中-公开
标题翻译：无线通信中的IFFT处理
公开(公告)号：WO2007115330A2
公开(公告)日：2007-10-11
申请号：PCT/US2007/066003
申请日：2007-04-04
申请人： QUALCOMM INCORPORATED , SUBRAHMANYAM, Jai N. , GANAPATHY, Chinnappa K. , VAN VEEN, Durk L. , BAI, Jinxia , COUSINEAU, Kevin Stuart , OH, Seokyong
发明人： SUBRAHMANYAM, Jai N. , GANAPATHY, Chinnappa K. , VAN VEEN, Durk L. , BAI, Jinxia , COUSINEAU, Kevin Stuart , OH, Seokyong
CPC分类号： H04L27/2626
摘要： Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.
摘要翻译：描述了用于执行IFFT流水线的技术。在一些方面，流水线通过具有具有第一，第二和第三部分的存储器的处理系统来实现，编码器被配置为以循环方式处理第一，第二和第三存储器部分中的每一个中的数据，IFFT被配置以循环方式处理第一，第二和第三部分中的每一个中的编码数据，以及后处理器，其被配置为以循环方式处理第一，第二和第三存储器部分中的每一个中的经IFFT处理的数据。

2. 发明申请

WO2007115328A2 IFFT PROCESSING IN WIRELESS COMMUNICATIONS 审中-公开
标题翻译：无线通信中的IFFT处理
公开(公告)号：WO2007115328A2
公开(公告)日：2007-10-11
申请号：PCT/US2007/066001
申请日：2007-04-04
申请人： QUALCOMM INCORPORATED , SUBRAHMANYAM, Jai N. , GANAPATHY, Chinnappa K. , VAN VEEN, Durk L. , BAI, Jinxia , COUSINEAU, Kevin Stuart , OH, Seokyong
发明人： SUBRAHMANYAM, Jai N. , GANAPATHY, Chinnappa K. , VAN VEEN, Durk L. , BAI, Jinxia , COUSINEAU, Kevin Stuart , OH, Seokyong
CPC分类号： H04L27/2626
摘要： Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.
摘要翻译：描述了用于执行IFFT流水线的技术。在一些方面，流水线通过具有具有第一和第二部分的存储器的处理系统来实现，编码器被配置为处理第一和第二存储器部分中的每一个中的数据;被配置为处理第一和第二部分中的编码数据的IFFT 存储器部分和后处理器，其被配置为在IFFT处理第二存储器部分中的编码数据时处理第一存储器部分中的IFFT处理的数据，后处理器被配置为以与编码器不同的时钟速度操作 IFFT。

3. 发明申请

WO2007115272A1 FORWARD ERROR CORRECTION IN A DISTRIBUTION SYSTEM 审中-公开
标题翻译：分配系统中的前向错误校正
公开(公告)号：WO2007115272A1
公开(公告)日：2007-10-11
申请号：PCT/US2007/065809
申请日：2007-04-02
申请人： QUALCOMM Incorporated , VAN VEEN, Durk L. , SUBRAHMANYAM, Jai N. , BAI, Jinxia , CHARI, Murali Ramaswamy
发明人： VAN VEEN, Durk L. , SUBRAHMANYAM, Jai N. , BAI, Jinxia , CHARI, Murali Ramaswamy
IPC分类号： H04L1/00
CPC分类号： H04L1/0061 , H04L1/0082 , H04L2001/0097
摘要： A multimedia distribution system is disclosed. The distribution system includes a transmitter unit that distributes content from a content provider to one or more wireless subscriber units. The transmitter unit includes a decoder configured to determine whether a plurality of incoming packets include one or more erasures, a transmitter configured to transmit the packets to a receiving unit, and an error detection code generator configured to generate an error detection code for each of the packets transmitted to the receiver unit, the error detection code being modified for each of the erased packets so that the receiver unit will be able to identify the erased packets.
摘要翻译：公开了一种多媒体分发系统。分配系统包括将内容从内容提供商分发到一个或多个无线用户单元的发射机单元。发射机单元包括解码器，其被配置为确定多个输入分组是否包括一个或多个擦除，被配置为将分组发送到接收单元的发射机，以及错误检测码发生器，被配置为生成每个发送到接收机单元的分组，针对每个被擦除的分组修改错误检测码，使得接收机单元将能够识别被擦除的分组。

4. 发明申请

WO2007115313A3 BUFFERING OF METRIC DATA 审中-公开
公开(公告)号：WO2007115313A3
公开(公告)日：2007-10-11
申请号：PCT/US2007/065985
申请日：2007-04-04
申请人： QUALCOMM Incorporated , BAI, Jinxia , GANAPATHY, Chinnappa, K. , SUN, Thomas
发明人： BAI, Jinxia , GANAPATHY, Chinnappa, K. , SUN, Thomas
IPC分类号： H04N5/00
摘要： Methods and apparatus for dynamic packet mapping. A method is provided for mapping metric data to produce a decodable packet associated with a channel. The method includes obtaining a channel identifier associated with metric data, determining an available buffer from a plurality of buffers based on the channel identifier, writing the metric data to the available buffer, detecting when a decodable packet is formed in a selected buffer of the plurality of buffers, and outputting the decodable packet from the selected buffer. An apparatus includes a plurality of buffers and mapping logic that is configured to obtain a channel identifier associated with metric data, determine an available buffer based on the channel identifier, write the metric data to the available buffer, detect when a decodable packet is formed in a selected buffer, and output the decodable packet from the selected buffer.

5. 发明申请

WO2007115284A1 METHODS AND APPARATUS FOR DYNAMIC PACKET REORDERING 审中-公开
标题翻译：动态分组重构的方法和装置
公开(公告)号：WO2007115284A1
公开(公告)日：2007-10-11
申请号：PCT/US2007/065904
申请日：2007-04-03
申请人： QUALCOMM Incorporated , BAI, Jinxia , GANAPATHY, Chinnappa, K. , SUN, Thomas
发明人： BAI, Jinxia , GANAPATHY, Chinnappa, K. , SUN, Thomas
IPC分类号： H04L1/00
CPC分类号： H04L27/2647 , H04L1/0045 , H04L1/0066 , H04L1/007 , H04L25/067
摘要： Methods and apparatus for dynamic packet reordering. In an aspect, a method is provided for processing slot data on-the-fly to produce decodable packets, wherein the slot data includes interleaved modulation symbols. The method includes de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols, calculating parallel streams of LLR metrics based on the stream of modulation symbols, and mapping the parallel streams of LLR metrics to produce a stream of decodable packets. In another aspect, an apparatus is provided the includes de-interleaving logic to de-interleave a stream of interleaved modulation symbols to produce a stream of modulation symbols, metric processing logic configured to produce parallel streams of LLR metrics based on the stream of modulation symbols, and mapping logic configured to map the parallel streams of LLR metrics to produce a stream of decodable packets.
摘要翻译：动态数据包重新排序的方法和装置。在一方面，提供了一种用于在运行中处理时隙数据以产生可解码分组的方法，其中时隙数据包括交织的调制符号。该方法包括对交织的调制符号的流进行解交织以产生调制符号流，基于调制符号流计算LLR度量的并行流，以及映射LLR度量的并行流以产生可解码分组流。在另一方面，提供了一种装置，其包括解交织逻辑以对交织的调制符号流进行解交织以产生调制符号流，度量处理逻辑被配置为基于调制符号流产生并行的LLR度量流以及配置成映射LLR度量的并行流的映射逻辑以产生可解码分组流。

6. 发明申请

WO2007056774A1 APPARATUS AND METHODS FOR ESTIMATING A SLEEP CLOCK FREQUENCY 审中-公开
标题翻译：用于估计休眠时钟频率的装置和方法
公开(公告)号：WO2007056774A1
公开(公告)日：2007-05-18
申请号：PCT/US2006/060747
申请日：2006-11-09
申请人： QUALCOMM INCORPORATED , WANG, Michael Mao , GANAPATHY, Chinnappa K. , BAI, Jinxia
发明人： WANG, Michael Mao , GANAPATHY, Chinnappa K. , BAI, Jinxia
IPC分类号： H04B1/16
CPC分类号： H04W52/029 , Y02D70/166
摘要： Apparatus and methods for estimating the frequency of a sleep or slow clock using a fast clock, such as a temperature compensated crystal oscillator. The disclosed apparatus include an estimator having a first counter that receives sleep clock synchronized pulses issuing each cycle of the sleep clock period, yet are synchronized to a fast clock. The slow clock synchronized pulses are counted up to a predetermined number; whereupon a full count signal is issued. A second counter receives the full count signal and increments each time the full count signal is received. A third counter counts fast clock cycles until the full count signal occurs. Based on the number of counts of the slow and fast clock cycles, the frequency of the slow clock may be determined using only the domain of the fast clock for performing the measurement thereby tying accuracy of the measurement to the accuracy of the fast clock. The disclosed apparatus also include an integrated circuit and a transceiver employing the disclosed estimator. Corresponding methods are also disclosed.
摘要翻译：使用诸如温度补偿晶体振荡器的快速时钟来估计睡眠或慢时钟频率的装置和方法。所公开的装置包括具有第一计数器的估计器，该第一计数器接收发出睡眠时钟周期的每个周期的休眠时钟同步脉冲，但是与快速时钟同步。慢时钟同步脉冲被计数到预定数目; 然后发出完整计数信号。第二计数器接收完全计数信号，并且每当接收到全计数信号时递增。第三个计数器计数快速时钟周期，直到发生完全计数信号。基于慢速和快速时钟周期的计数次数，可以仅使用用于执行测量的快速时钟的域来确定慢时钟的频率，从而将测量的精度与快速时钟的精度相结合。所公开的装置还包括采用所公开的估计器的集成电路和收发器。还公开了相应的方法。

7. 发明申请

WO2007131023A1 PARALLEL BIT INTERLEAVER FOR A WIRELESS SYSTEM 审中-公开
标题翻译：用于无线系统的并行比特交换机
公开(公告)号：WO2007131023A1
公开(公告)日：2007-11-15
申请号：PCT/US2007/068003
申请日：2007-05-02
申请人： QUALCOMM Incorporated , BAI, Jinxia , SUN, Thomas
发明人： BAI, Jinxia , SUN, Thomas
IPC分类号： H03M13/27 , H04L1/00
CPC分类号： H04L1/0071 , H04L1/0018 , H04L1/0066 , H04L2001/0093
摘要： Systems and methods are provided to process wireless data packets. A method includes determining a subset of data bits to be processed at a wireless transmitter and employing a clock edge to store the data. The clock edge allows parallel mapping of at least two bits from the subset of data bits into an interleaver memory per a given clock edge. From the memory, other encoding and scrambling processes are applied before transmitting the data packets across a wireless network.
摘要翻译：提供系统和方法来处理无线数据分组。一种方法包括确定要在无线发射机处理的数据比特的子集，并采用时钟边缘来存储数据。时钟沿允许从每个给定时钟沿到数据比特子集的至少两个比特到交织器存储器的并行映射。从存储器中，在通过无线网络发送数据分组之前应用其他编码和加扰处理。

8. 发明申请

WO2011019741A1 SYSTEMS AND METHODS FOR CLOCK CORRECTION 审中-公开
标题翻译：用于时钟校正的系统和方法
公开(公告)号：WO2011019741A1
公开(公告)日：2011-02-17
申请号：PCT/US2010/045058
申请日：2010-08-10
申请人： QUALCOMM INCORPORATED , BAI, Jinxia , LI, Linbo
发明人： BAI, Jinxia , LI, Linbo
IPC分类号： H04L7/00 , G06F1/04
CPC分类号： H04L7/0008 , G06F1/12 , H04L7/0025
摘要： A method, apparatus and system for correcting different clock domains are disclosed. The disclosed implementations correct a second clock domain by making reference to a resampling filter, or similar device, used to correct a first clock domain. The implementations thereby facilitate clock correction using fewer or a different variety of elements.
摘要翻译：公开了一种用于校正不同时钟域的方法，装置和系统。所公开的实现通过参考用于校正第一时钟域的重采样滤波器或类似装置来校正第二时钟域。因此，这些实施方式使用较少或不同种类的元件便于时钟校正。

9. 发明申请

WO2006076599A1 MULTIRESOLUTION MODULATION USING VARIABLE EUCLIDEAN DISTANCE RATIO AND BLIND RECEIVER 审中-公开
标题翻译：使用可变的EUCLIDEAN距离比和盲接收机的多分辨率调制
公开(公告)号：WO2006076599A1
公开(公告)日：2006-07-20
申请号：PCT/US2006/001285
申请日：2006-01-11
申请人： QUALCOMM INCORPORATED , LING, Fuyun , CHUNG, Seong Taek , SUN, Thomas , BAI, Jinxia
发明人： LING, Fuyun , CHUNG, Seong Taek , SUN, Thomas , BAI, Jinxia
IPC分类号： H04L27/34
CPC分类号： H04L25/067 , H04L25/03171 , H04L27/2601 , H04L27/3488 , H04L27/38 , H04L2025/0342
摘要： A system and method are provided for generating bit log likelihood ratio (LLR) values for two-layered Quadrature Phase-Shift Keying (QPSK) turbo decoding in a wireless communications user terminal (UT). The method includes receiving a two-layered QPSK signal with an energy ratio that is unknown, but typically defined as either k 1 2 or k 2 2 . The method selects a mismatched energy ratio ( k 2 ) between k 1 2 and k 2 2 , and generating bit LLR values for two-layered QPSK turbo decoding, using the mismatched k 2 energy ratio. For example, if the received two-layered QPSK signal is known to have an energy ratio of about 4 or about 6.25. Then, k 2 is selected to be about 5.0625. Alternately stated, the mismatched k 2 energy ratio in selected by determining the approximate midpoint between k 1 2 and k 2 2 .
摘要翻译：提供了一种用于在无线通信用户终端（UT）中生成用于双层正交相移键控（QPSK）turbo解码的比特对数似然比（LLR）值的系统和方法。该方法包括以未知的能量比接收双向QPSK信号，但通常被定义为k1≤2或k2 <2>。该方法选择不匹配的能量比（k ^2）

10. 发明公开

EP1946450A1 APPARATUS AND METHODS FOR ESTIMATING A SLEEP CLOCK FREQUENCY 审中-公开
标题翻译： VORRICHTUNGEN UND VERFAHREN ZURSCHÄTZUNGEINER SLEEP-TAKTFREQUENZ
公开(公告)号：EP1946450A1
公开(公告)日：2008-07-23
申请号：EP06839807.2
申请日：2006-11-09
申请人： QUALCOMM Incorporated
发明人： WANG, Michael Mao , GANAPATHY, Chinnappa K. , BAI, Jinxia
IPC分类号： H04B1/16
CPC分类号： H04W52/029 , Y02D70/166
摘要： Apparatus and methods for estimating the frequency of a sleep or slow clock using a fast clock, such as a temperature compensated crystal oscillator. The disclosed apparatus include an estimator having a first counter that receives sleep clock synchronized pulses issuing each cycle of the sleep clock period, yet are synchronized to a fast clock. The slow clock synchronized pulses are counted up to a predetermined number; whereupon a full count signal is issued. A second counter receives the full count signal and increments each time the full count signal is received. A third counter counts fast clock cycles until the full count signal occurs. Based on the number of counts of the slow and fast clock cycles, the frequency of the slow clock may be determined using only the domain of the fast clock for performing the measurement thereby tying accuracy of the measurement to the accuracy of the fast clock. The disclosed apparatus also include an integrated circuit and a transceiver employing the disclosed estimator. Corresponding methods are also disclosed.
摘要翻译：使用诸如温度补偿晶体振荡器的快速时钟来估计睡眠或慢时钟的频率的装置和方法。所公开的装置包括具有第一计数器的估计器，该第一计数器接收发出睡眠时钟周期的每个周期的睡眠时钟同步脉冲，但是与快速时钟同步。慢时钟同步脉冲被计数到预定数量; 于是发出完整计数信号。第二个计数器接收完整的计数信号，并在每次接收到全部计数信号时递增。第三个计数器计数快速时钟周期，直到发生完全计数信号。基于慢速和快速时钟周期的计数次数，可以仅使用用于执行测量的快速时钟的域来确定慢时钟的频率，从而将测量的精度与快速时钟的精度相结合。所公开的装置还包括采用所公开的估计器的集成电路和收发器。还公开了相应的方法。

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