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1. 发明申请

WO2006052720A1 INTEGRATED CIRCUIT WITH ADAPTIVE SPEED BINNING 审中-公开
标题翻译：集成电路与自适应速度绑定
公开(公告)号：WO2006052720A1
公开(公告)日：2006-05-18
申请号：PCT/US2005/039952
申请日：2005-11-04
申请人： QUALCOMM INCORPORATED , PATEL, Jagrut, V. , PRABHAKARAN, Rajeev , KAPOOR, Sanat , BULLARD, Gregory
发明人： PATEL, Jagrut, V. , PRABHAKARAN, Rajeev , KAPOOR, Sanat , BULLARD, Gregory
IPC分类号： G06F1/08
CPC分类号： G11C7/22 , G06F1/08 , G11C7/222 , G11C2207/2254 , H03K2005/00058
摘要： Systems and techniques are disclosed relating to adapting the frequency of an electronic device comprising an integrated circuit and an electronic component to improve performance. The integrated circuit determines a set of frequency plans, each corresponding to a distribution of delay range highest passing values and one of a set of frequencies at which the electronic device can operate. Based on communication with the electronic component, the integrated circuit implements a preferred frequency plan.
摘要翻译：公开了涉及适应包括集成电路和电子部件的电子设备的频率以提高性能的系统和技术。集成电路确定一组频率计划，每个频率计划对应于延迟范围最高通过值的分布和电子设备可以在其中操作的一组频率中的一个。基于与电子部件的通信，集成电路实现优选的频率计划。

2. 发明申请

WO2005052771A1 CALIBRATING AN INTEGRATED CIRCUIT TO AN ELECTRONIC DEVICE 审中-公开
标题翻译：将集成电路校准到电子设备
公开(公告)号：WO2005052771A1
公开(公告)日：2005-06-09
申请号：PCT/US2004/039691
申请日：2004-11-24
申请人： QUALCOMM INCORPORATED , PATEL, Jagrut V. , CHUN, Dexter Tamio , BULLARD, Gregory , SANKURATRI, Raghu , PRABHAKARAN, Rajeev , KAPOOR, Sanat
发明人： PATEL, Jagrut V. , CHUN, Dexter Tamio , BULLARD, Gregory , SANKURATRI, Raghu , PRABHAKARAN, Rajeev , KAPOOR, Sanat
IPC分类号： G06F1/14
CPC分类号： G01R35/005
摘要： Systems and techniques are disclosed relating to calibrating an integrated circuit to an electronic component in order to compensate for process, voltage on temperature variations. The systems and techniques include an integrated circuit configured to generate a system clock and an external clock having a programmable delay from the system clock. The integrated circuit may also be configured to provide the external clock to the electronic component to support communications therewith, communicate with the electronic component, and calibrate the external clock delay as a function of the communications.
摘要翻译：公开了关于将集成电路校准到电子部件的系统和技术，以便补偿过程，温度变化上的电压。该系统和技术包括被配置为产生系统时钟的集成电路和具有来自系统时钟的可编程延迟的外部时钟。集成电路还可以被配置为向电子部件提供外部时钟以支持与其通信，与电子部件通信，并且根据通信校准外部时钟延迟。

3. 发明申请

WO2006052929A1 ADAPTIVE MEMORY CALIBRATION USING BINS 审中-公开
标题翻译：使用BINS的自适应内存校准
公开(公告)号：WO2006052929A1
公开(公告)日：2006-05-18
申请号：PCT/US2005/040363
申请日：2005-11-07
申请人： QUALCOMM INCORPORATED , PATEL, Jagrut Viliskumar , BULLARD, Gregory , KAPOOR, Sanat
发明人： PATEL, Jagrut Viliskumar , BULLARD, Gregory , KAPOOR, Sanat
IPC分类号： G01R31/3193 , G11C29/50
CPC分类号： G11C7/22 , G01R31/3193 , G01R31/31937 , G11C7/04 , G11C7/222 , G11C11/401 , G11C29/022 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2207/2254
摘要： An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and the external clock in which the integrated circuit and the electronic component can communicate, and program the external clock with one of a plurality of predetermined delay values based on the delay range.
摘要翻译：电子设备包括电子部件和集成电路，其中集成电路被配置为产生系统时钟和具有来自系统时钟的可编程延迟的外部时钟，将外部时钟提供给电子部件，确定电子部件之间的延迟范围系统时钟和集成电路和电子部件可以通信的外部时钟，并且基于延迟范围以多个预定延迟值中的一个对外部时钟进行编程。

4. 发明申请

WO2007059443A2 CLOCK SIGNAL GENERATION TECHNIQUES FOR MEMORIES THAT DO NOT GENERATE A STROBE 审中-公开
标题翻译：不产生STROBE的记忆的时钟信号发生技术
公开(公告)号：WO2007059443A2
公开(公告)日：2007-05-24
申请号：PCT/US2006/060797
申请日：2006-11-10
申请人： QUALCOMM INCORPORATED , SRINIVAS, Vaishnav , KAPOOR, Sanat , MADDALI, Srinivas , MOHAN, Vivek
发明人： SRINIVAS, Vaishnav , KAPOOR, Sanat , MADDALI, Srinivas , MOHAN, Vivek
IPC分类号： G06F13/16 , G11C7/10
CPC分类号： G11C7/1051
摘要： This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.
摘要翻译：本公开描述了用于存储器控制器的时钟电路。所描述的电路使用处理器时钟信号来产生用于在对存储器的写入操作期间使用的输入时钟信号，或者产生用于在来自存储器的读取操作期间使用的反馈时钟信号。该电路特别适用于包括不产生频闪的存储器的移动无线设备。时钟电路可以包括与电阻器元件串联的驱动器，该电阻器产生用于输入到存储器的输入时钟信号，以及与产生用于从存储器输出的反馈时钟信号的接收器串联的电阻器 - 电容器（RC）滤波器其中在所述驱动器和所述电阻器元件之间分接所述RC滤波器的输入。

5. 发明公开

EP1815310A1 INTEGRATED CIRCUIT WITH ADAPTIVE SPEED BINNING 有权
标题翻译：集成电路与自适应速度绑定
公开(公告)号：EP1815310A1
公开(公告)日：2007-08-08
申请号：EP05815929.4
申请日：2005-11-04
申请人： QUALCOMM INCORPORATED
发明人： PATEL, Jagrut, V. , PRABHAKARAN, Rajeev , KAPOOR, Sanat , BULLARD, Gregory
IPC分类号： G06F1/08
CPC分类号： G11C7/22 , G06F1/08 , G11C7/222 , G11C2207/2254 , H03K2005/00058
摘要： Systems and techniques are disclosed relating to adapting the frequency of an electronic device comprising an integrated circuit and an electronic component to improve performance. The integrated circuit determines a set of frequency plans, each corresponding to a distribution of delay range highest passing values and one of a set of frequencies at which the electronic device can operate. Based on communication with the electronic component, the integrated circuit implements a preferred frequency plan.
摘要翻译：公开了涉及调整包括集成电路和电子组件的电子设备的频率以改善性能的系统和技术。集成电路确定一组频率计划，每个频率计划对应于延迟范围最高通过值的分布和电子设备可以操作的一组频率中的一个。基于与电子组件的通信，集成电路实现优选的频率计划。

6. 发明申请

WO2019089132A1 METHODS AND SYSTEMS TO BROADCAST SENSOR OUTPUTS IN AN AUTOMOTIVE ENVIRONMENT 审中-公开
公开(公告)号：WO2019089132A1
公开(公告)日：2019-05-09
申请号：PCT/US2018/050287
申请日：2018-09-10
申请人： QUALCOMM INCORPORATED
发明人： CHU, Jeffrey, Hao , GULATI, Rahul , HARDACKER, Robert , JONG, Alex , KAKOEE, Reza , KATIBIAN, Behnam , SAXENA, Anshuman , VISHIN, Sanjay , KAPOOR, Sanat
IPC分类号： G01S17/93 , B60W50/00
摘要： Methods and systems to broadcast sensor outputs in an automotive environment allow sensors such as cameras (108) to output relatively unprocessed (raw) data to two or more different processing circuits (406, 412) where the processing circuits are located in separate and distinct embedded control units (ECUs). A first one of the two or more different processing circuits processes the raw data for human consumption. A second one of the two or more different processing circuits processes the raw data for machine utilization such as for autonomous driving functions. Such an arrangement allows for greater flexibility in utilization of the data from the sensors without imposing undue latency in the processing stream and without compromising key performance indices for human use and machine use. Each camera 108(1)-108(M) of camera system (400) is associated with an embedded control unit (ECU) (402(1)-402(M)), each ECU including a serializer/deserializer (404(1)-404(M)). Cameras (108(1)) and (108(2)), have no operator function and thus send their output to a computer vision ECU (406) and, in particular, to a deserializer/ serializer (408) therein for processing by a computer vision system on a chip (SoC) (410). Cameras (108(3)-108(M)) are useful for both operator assistance as well as autonomous driver assistance system, ADAS, functions. Serializers/deserializers (404(3)-404(M)) include dual-port outputs that provide raw image data not only to the computer vision ECU (406), but also to an infotainment ECU (412). The computer vision ECU (406) is separate and distinct from the infotainment ECU (412). A deserializer/serializer (414) receives and deserializes the data before passing the data to an infotainment SoC (416) having an associated display (418). This arrangement allows for relatively low latency as the data is not processed by one circuit and then passed to the other circuit for further processing.

7. 发明申请

WO2014011490A1 METHOD AND APPARATUS FOR CHARACTERIZING POWER SUPPLY IMEPDANCE FOR POWER DELIVERY NETWORKS 审中-公开
标题翻译：用于表征电力输送网络的电源IMEPD的方法和装置
公开(公告)号：WO2014011490A1
公开(公告)日：2014-01-16
申请号：PCT/US2013/049392
申请日：2013-07-03
申请人： QUALCOMM INCORPORATED
发明人： KAPOOR, Sanat , EINSMANN, Christopher F. , TRUJILLO, Alfonso T.
IPC分类号： G06G7/26 , G01R31/00
CPC分类号： G06G7/26
摘要： A method and apparatus for generating an arbitrary current waveform for use in characterizing power supply impedance for power delivery networks are provided. The method begins by providing an arbitrary waveform as an input to a test circuit. The current and voltage at an output of a device under test in then examined. A frequency is then swept through a pre-determined range; and the frequency of the arbitrary voltage waveform is changed to match a predetermined frequency and impedance point.
摘要翻译：提供一种用于产生用于表征供电网络的电源阻抗的任意电流波形的方法和装置。该方法开始于提供任意波形作为测试电路的输入。然后检查的被测器件的输出端的电流和电压。然后将频率扫过预定范围; 并且任意电压波形的频率被改变以匹配预定的频率和阻抗点。

8. 发明申请

WO2019135871A1 WIDE-BAND WILKINSON DIVIDER 审中-公开
公开(公告)号：WO2019135871A1
公开(公告)日：2019-07-11
申请号：PCT/US2018/065210
申请日：2018-12-12
申请人： QUALCOMM INCORPORATED
发明人： FRANK, Wolfgang , GONG, Qizhi , WALTER, Scott , KAPOOR, Sanat
IPC分类号： H01P5/16 , H01P3/08 , H01P1/203
摘要： Certain aspects of the present disclosure provide a circuit for dividing or combining power. The circuit generally includes a Wilkinson power divider, a first capacitive element, and a first resistive element coupled in parallel with the first capacitive element, wherein the first capacitive element and the first resistive element are coupled between a first port of the circuit and a first port of the Wilkinson power divider.

9. 发明授权

EP1815310B1 INTEGRATED CIRCUIT WITH ADAPTIVE SPEED BINNING 有权
公开(公告)号：EP1815310B1
公开(公告)日：2017-06-28
申请号：EP05815929.4
申请日：2005-11-04
申请人： QUALCOMM INCORPORATED
发明人： PATEL, Jagrut, V. , PRABHAKARAN, Rajeev , KAPOOR, Sanat , BULLARD, Gregory
IPC分类号： G06F1/08 , G11C7/22 , H03K5/00
CPC分类号： G11C7/22 , G06F1/08 , G11C7/222 , G11C2207/2254 , H03K2005/00058

10. 发明授权

EP1812804B1 ADAPTIVE MEMORY CALIBRATION USING BINS 有权
标题翻译：自适应SPEICHERKALIBRATION使用槽
公开(公告)号：EP1812804B1
公开(公告)日：2009-04-29
申请号：EP05817276.8
申请日：2005-11-07
申请人： QUALCOMM INCORPORATED
发明人： PATEL, Jagrut Viliskumar , BULLARD, Gregory , KAPOOR, Sanat
IPC分类号： G01R31/3193
CPC分类号： G11C7/22 , G01R31/3193 , G01R31/31937 , G11C7/04 , G11C7/222 , G11C11/401 , G11C29/022 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2207/2254
摘要： An electronic device comprises an electronic component and an integrated circuit, wherein the integrated circuit is configured to generate a system clock and an external clock having a programmable delay from the system clock, provide the external clock to the electronic component, determine a delay range between system clock and the external clock in which the integrated circuit and the electronic component can communicate, and program the external clock with one of a plurality of predetermined delay values based on the delay range.

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