专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2009129283A1 MANUFACTURING METHOD OF A MAGNETIC TUNNEL JUNCTION ELEMENT USING TWO MASKS 审中-公开
标题翻译：使用两个掩模的磁性隧道结构元件的制造方法
公开(公告)号：WO2009129283A1
公开(公告)日：2009-10-22
申请号：PCT/US2009/040612
申请日：2009-04-15
申请人： QUALCOMM INCORPORATED , KANG, Seung, H. , LI, Xia , GU, Shiqun , NOWAK, Matthew, M.
发明人： KANG, Seung, H. , LI, Xia , GU, Shiqun , NOWAK, Matthew, M.
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L43/08 , G11C11/161 , H01L43/12
摘要： A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer (36) containing an exposed first interconnect metallization, (37) a first electrode, (30) a fixed magnetization layer, (32) a tunneling barrier layer, (12) a free magnetization layer (11) and a second electrode (6). An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer (40) encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode (15) is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer (8) covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.
摘要翻译：用于使用两个掩模形成用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）的方法包括在包含暴露的第一互连金属化的层间介质层（36）上沉积（37）第一电极，（30）固定磁化层，（32）隧道势垒层，（12）自由磁化层（11）和第二电极（6）。包括隧道势垒层，自由层和第二电极的MTJ结构通过第一掩模限定在第一互连金属化之上。第一钝化层（40）封装MTJ结构，留下第二电极。沉积与第二电极接触的第三电极（15）。使用第二掩模来图案化包括第三电极，第一钝化层，固定磁化层和第一电极的较大结构。第二介电钝化层（8）覆盖被蚀刻的多个层，第一层间介质层和第一互连金属化层。

2. 发明申请

WO2010011448A2 PREDICTIVE MODELING OF INTERCONNECT MODULES FOR ADVANCED ON-CHIP INTERCONNECT TECHNOLOGY 审中-公开
标题翻译：用于高级片上互连技术的互连模块的预测建模
公开(公告)号：WO2010011448A2
公开(公告)日：2010-01-28
申请号：PCT/US2009/047668
申请日：2009-06-17
申请人： QUALCOMM INCORPORATED , LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung, H. , NOWAK, Matthew
发明人： LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung, H. , NOWAK, Matthew
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.
摘要翻译：计算机程序产品估计半导体集成电路（IC）的互连结构的性能。程序产品包括在计算机上执行的代码，用于基于考虑到互连结构的多层的输入数据来计算互连结构的至少一个电特性。电气特性可以是电容，电阻和/或电感。电容可以基于多个分量，包括边缘电容分量，端子电容分量和耦合电容分量。

3. 发明申请

WO2009131944A1 STT MRAM MAGNETIC TUNNEL JUNCTION ARCHITECTURE AND INTEGRATION 审中-公开
标题翻译： STT MRAM磁铁隧道结构和集成
公开(公告)号：WO2009131944A1
公开(公告)日：2009-10-29
申请号：PCT/US2009/041132
申请日：2009-04-20
申请人： QUALCOMM INCORPORATED , KANG, Seung, H. , LI, Xia , GU, Shiqun , LEE, Kangho , ZHU, Xiaochun
发明人： KANG, Seung, H. , LI, Xia , GU, Shiqun , LEE, Kangho , ZHU, Xiaochun
IPC分类号： H01L43/08 , H01L27/22 , H01L43/12
CPC分类号： H01L27/222 , H01L43/08 , H01L43/12
摘要： A magnetic tunnel junction (MTJ) device (400) for a magnetic random access memory (MRAM) in a semiconductor back-end-of-line (BEOL) process flow includes a first metal interconnect (401) for communicating with at least one control device and a first electrode (406) for coupling to the first metal interconnect through a via formed in a dielectric passivation barrier (404) using a first mask. The device also includes an MTJ stack (407, 408, 409) for storing data coupled to the first electrode, a portion of the MTJ stack having lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode (410) is coupled to the MTJ stack and also has a same lateral dimension as defined by the second mask. The first electrode (406) and a portion (407) of the MTJ stack. are defined by a third mask. A second metal interconnect (415) is coupled to the second electrode and at least one other control device.
摘要翻译：用于半导体后端（BEOL）处理流程中的磁随机存取存储器（MRAM）的磁性隧道结（MTJ）装置（400）包括用于与至少一个控制器器件和第一电极（406），用于通过使用第一掩模在介电钝化屏障（404）中形成的通孔耦合到第一金属互连。该装置还包括用于存储耦合到第一电极的数据的MTJ堆叠（407,408,409），MTJ堆叠的一部分具有基于第二掩模的侧向尺寸。由第二掩模限定的部分在接触通孔之上。第二电极（410）耦合到MTJ堆叠并且还具有与第二掩模所限定的相同的横向尺寸。第一电极（406）和MTJ叠层的一部分（407）。由第三个掩码定义。第二金属互连（415）耦合到第二电极和至少一个其他控制装置。

4. 发明申请

WO2011075491A1 VIA STRUCTURE INTEGRATED IN ELECTRONIC SUBSTRATE 审中-公开
标题翻译：通过集成在电子基板中的结构
公开(公告)号：WO2011075491A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060362
申请日：2010-12-14
申请人： QUALCOMM Incorporated , LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung H. , KING, Ming-Chu
发明人： LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung H. , KING, Ming-Chu
IPC分类号： H01L23/552 , H01L23/66 , H01L23/498 , H01L23/48 , H01L23/64 , H05K1/02
CPC分类号： H01L23/552 , H01L23/14 , H01L23/49827 , H01L23/645 , H01L23/66 , H01L2223/6616 , H01L2223/6622 , H01L2223/6638 , H01L2924/0002 , H01L2924/3011 , H05K1/0222 , H05K1/0245 , H05K3/4602 , H05K3/4644 , H05K2201/09809 , Y10T29/49117 , H01L2924/00
摘要： A system of via structures disposed in a substrate. The system includes a first via structure that comprises an outer conductive layer, an inner insulating layer, and an inner conductive layer disposed in the substrate. The outer conductive layer separates the inner insulating layer and the substrate and the inner insulating layer separates the inner conductive layer and the outer conductive layer. A first signal of a first complementary pair passes through the inner conductive layer and a second signal of the first complementary pair passes through the outer conductive layer. In different embodiments, a method of forming a via structure in an electronic substrate is provided.
摘要翻译：设置在基板中的通孔结构的系统。该系统包括第一通孔结构，其包括外导电层，内绝缘层和设置在基板中的内导电层。外部导电层分离内部绝缘层和基板，内部绝缘层分离内部导电层和外部导电层。第一互补对的第一信号通过内导电层，第一互补对的第二信号通过外导电层。在不同的实施例中，提供了一种在电子衬底中形成通孔结构的方法。

5. 发明申请

WO2009079662A1 MAGNETIC TUNNEL JUNCTION DEVICE WITH SEPARATE READ AND WRITE PATHS 审中-公开
标题翻译：具有单独读取和写入功能的磁性隧道连接装置
公开(公告)号：WO2009079662A1
公开(公告)日：2009-06-25
申请号：PCT/US2008/087748
申请日：2008-12-19
申请人： QUALCOMM Incorporated , ZHU, Xiaochun , GU, Shiqun , LI, Xia , KANG, Seung H.
发明人： ZHU, Xiaochun , GU, Shiqun , LI, Xia , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , Y10S977/933 , Y10S977/935
摘要： In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path (102) coupled to the MTJ structure and a write path (104) coupled to the MTJ structure. The write path (104) is separate from the read path (102). The device in substance comprises a pair of serially coupled MTJ structures (106, 108), whereby the read path (102) comprises only one of the MTJ structure (108). This provides for combined improved read margin and improved write margin.
摘要翻译：在一个实施例中，公开了一种包括磁隧道结（MTJ）结构的装置。该设备还包括耦合到MTJ结构的读取路径（102）和耦合到MTJ结构的写入路径（104）。写入路径（104）与读取路径（102）分离。实质的装置包括一对串联耦合的MTJ结构（106,108），由此读路径（102）仅包括MTJ结构（108）中的一个。这提供了组合改进的读取余量和改进的写入余量。

6. 发明申请

WO2011116325A1 THROUGH GLASS VIA MANUFACTURING PROCESS 审中-公开
标题翻译：通过制造过程的玻璃
公开(公告)号：WO2011116325A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/029057
申请日：2011-03-18
申请人： QUALCOMM Incorporated , GU, Shiqun , LI, Xia , LI, Yiming
发明人： GU, Shiqun , LI, Xia , LI, Yiming
IPC分类号： H01L21/48 , H01L23/15 , H01L23/498
CPC分类号： H01L23/15 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H05K3/0041 , Y10T428/24273 , H01L2924/00
摘要： Fabrication of a through glass via in a relatively thick glass substrate includes patterning a through glass via hard mask on a surface of the glass substrate. The fabrication also includes wet etching a portion of the glass substrate, through the hard mask, to create a partial through glass via. The wet etching may involve applying a vapor of an oxide etch chemical, such as HF and XeF6, or applying a wet oxide etch chemical, such as HF and XeF6. The fabrication further includes passivating the etched partial through glass via, removing bottom passivation from the partial through glass via, and repeating the etching, passivating and removing to create the through glass via. The resulting through glass via has a scalloped side wall, a vertical profile and a high aspect ratio.
摘要翻译：在相对厚的玻璃基板中制造直通玻璃通孔包括在玻璃基板的表面上通过硬掩模图案化通孔玻璃。该制造还包括通过硬掩模湿法蚀刻玻璃基底的一部分，以产生部分透过玻璃通孔。湿蚀刻可以包括施加氧化物蚀刻化学品的蒸气，例如HF和XeF 6，或者施加湿氧化物蚀刻化学品，例如HF和XeF 6。该制造还包括钝化蚀刻的部分通过玻璃通孔，从部分通过玻璃通孔去除底部钝化，并重复蚀刻，钝化和去除以产生通孔玻璃通孔。所产生的通过玻璃通孔具有扇形侧壁，垂直轮廓和高纵横比。

7. 发明申请

WO2012112619A1 METHODS OF INTEGRATED SHIELDING INTO MTJ DEVICE FOR MRAM 审中-公开
标题翻译：用于MRAM的MTJ器件的集成屏蔽方法
公开(公告)号：WO2012112619A1
公开(公告)日：2012-08-23
申请号：PCT/US2012/025133
申请日：2012-02-14
申请人： QUALCOMM Incorporated , CHEN, Wei-Chuan , LI, Xia , KANG, Seung H.
发明人： CHEN, Wei-Chuan , LI, Xia , KANG, Seung H.
IPC分类号： G11C11/16 , H01L27/22 , H01L43/08
CPC分类号： G11C11/16 , G11C11/161 , H01L23/552 , H01L27/11502 , H01L27/11507 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus for shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via.
摘要翻译：提供了用于屏蔽非易失性存储器的方法和装置，例如屏蔽磁性隧道结（MTJ）装置与磁通量。在一个示例中，屏蔽层邻近MTJ器件的电极形成，使得屏蔽层基本上围绕电极的表面，并且金属线耦合到屏蔽层。金属线可以通过通孔耦合到屏蔽层。

8. 发明申请

WO2012019135A2 MRAM DEVICE AND INTEGRATION TECHNIQUES COMPATIBLE WITH LOGIC INTEGRATION 审中-公开
标题翻译： MRAM设备和集成技术兼容逻辑整合
公开(公告)号：WO2012019135A2
公开(公告)日：2012-02-09
申请号：PCT/US2011/046811
申请日：2011-08-05
申请人： QUALCOMM INCORPORATED , LI, Xia , ZHU, Xiaochun , KANG, Seung H.
发明人： LI, Xia , ZHU, Xiaochun , KANG, Seung H.
IPC分类号： H01L27/22
CPC分类号： H01L43/12 , B82Y10/00 , G11C11/161 , H01L27/228 , H01L43/08
摘要： A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.
摘要翻译：半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁隧道结（MTJ）存储元件。盖层将公共IMD层与顶部和底部IMD层分开。顶部和底部电极耦合到MTJ存储元件。金属与电极的连接分别通过分离盖层中的通孔形成在顶部和底部IMD层中。或者，分离盖层是凹进的并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。通过用金属岛和隔离帽隔离与MTJ存储元件的金属连接来实现与公共IMD层中顶部电极的金属连接。

9. 发明申请

WO2012018918A2 GENERATING A NON-REVERSIBLE STATE AT A BITCELL HAVING A FIRST MAGNETIC TUNNEL JUNCTION AND A SECOND MAGNETIC TUNNEL JUNCTION 审中-公开
标题翻译：在具有第一磁性隧道接头和第二磁性隧道接头的位置处产生不可逆状态
公开(公告)号：WO2012018918A2
公开(公告)日：2012-02-09
申请号：PCT/US2011/046429
申请日：2011-08-03
申请人： QUALCOMM INCORPORATED , RAO, Hari, M. , KIM, Jung, Pill , KANG, Seung, H. , ZHU, Xiaochun , KIM, Tae, Hyun , LEE, Kangho , LI, Xia , HSU, Wah, Nam , HAO, Wuyang , SUH, Jungwon , YU, Nicholas, K. , NOWAK, Matthew, Michael , MILLENDORF, Steven, M. , ASHKENAZI, Asaf
发明人： RAO, Hari, M. , KIM, Jung, Pill , KANG, Seung, H. , ZHU, Xiaochun , KIM, Tae, Hyun , LEE, Kangho , LI, Xia , HSU, Wah, Nam , HAO, Wuyang , SUH, Jungwon , YU, Nicholas, K. , NOWAK, Matthew, Michael , MILLENDORF, Steven, M. , ASHKENAZI, Asaf
IPC分类号： G11C17/16
CPC分类号： G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
摘要： A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.
摘要翻译：在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。存储器件包括具有第一MTJ和第二MTJ的位单元以及被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个而在位单元处产生不可逆状态的编程电路。

10. 发明申请

WO2012009524A2 MAGNETIC STORAGE ELEMENT UTILIZING IMPROVED PINNED LAYER STACK 审中-公开
标题翻译：磁性储存元件利用改进的PINNED层堆叠
公开(公告)号：WO2012009524A2
公开(公告)日：2012-01-19
申请号：PCT/US2011/043992
申请日：2011-07-14
申请人： QUALCOMM INCORPORATED , CHEN, Wei-Chuan , KANG, Seung H. , ZHU, Xiaochun , LI, Xia
发明人： CHEN, Wei-Chuan , KANG, Seung H. , ZHU, Xiaochun , LI, Xia
IPC分类号： H01L43/08
CPC分类号： H01L43/08
摘要： A magnetic tunnel junction (MTJ) storage element may comprise a pinned layer stack and a first functional layer. The pinned layer stack is formed of a plurality of layers comprising a bottom pinned layer, a coupling layer, and a top pinned layer. The first functional layer is disposed in the bottom pinned layer or the top pinned layer.
摘要翻译：磁性隧道结（MTJ）存储元件可以包括钉扎层堆叠和第一功能层。钉扎层堆叠由包括底部钉扎层，耦合层和顶部钉扎层的多个层形成。第一功能层设置在底部钉扎层或顶部钉扎层中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式