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1. 发明申请

WO2017142650A1 SYSTEMS AND METHODS FOR INDIVIDUALLY CONFIGURING DYNAMIC RANDOM ACCESS MEMORIES SHARING A COMMON COMMAND ACCESS BUS 审中-公开
标题翻译：用于单独配置动态随机访问记忆的系统和方法，共享一个公共命令访问总线
公开(公告)号：WO2017142650A1
公开(公告)日：2017-08-24
申请号：PCT/US2017/013141
申请日：2017-01-12
申请人： QUALCOMM INCORPORATED
发明人： AQUIL, Farrukh , DROP, Michael , SRINIVAS, Vaishnav , CLOVIS, Philip
IPC分类号： G06F13/16
CPC分类号： G11C11/4093 , G06F13/1678 , G06F13/1694 , G06F13/4282 , G11C7/1072 , G11C11/4076 , G11C11/4082 , G11C11/4087 , G11C11/4096
摘要： Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.
摘要翻译：公开了用于在个人计算设备（PCD）中配置动态随机存取存储器（DRAM）的系统和方法。示例性方法包括提供与第一DRAM和第二DRAM通信的共享命令访问（CA）总线。在第一DRAM和第二DRAM处接收来自片上系统（SoC）的第一命令。第一DRAM的解码器响应于所接收的第一命令确定是否屏蔽模式寄存器写入（MRW）。在第一DRAM和第二DRAM上通过共享CA总线接收包含配置信息的第二命令。响应于第一DRAM的解码器的确定，所接收的MRW被第一DRAM忽略或实现。

2. 发明申请

WO2010014477A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平输入/输出电路
公开(公告)号：WO2010014477A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/051419
申请日：2009-07-22
申请人： QUALCOMM INCORPORATED , SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/00315 , H03K19/018507 , H03K19/018585
摘要： An interface input (fig.2: 220) has an input circuit (fig.10: 221) adapted to receive input signal levels (padloc) higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit (fig.10: 221) shifts the level of the input signal (padloc) to a desired signal level. A keeper circuit (keeper: pull up 1011; pull down 1012) is coupled to the input circuit and maintains trigger levels of the shifted signals (lvl_dn_int) consistent with the input signal level (padloc).
摘要翻译：接口输入（图2：220）具有适于接收高于主机电路的电子部件可以可靠地处理的最大信号电平的输入信号电平（padloc）的输入电路（图10：221）。输入电路（图10：221）将输入信号（padloc）的电平移动到期望的信号电平。保持器电路（保持器：上拉1011;下拉1012）耦合到输入电路，并保持与输入信号电平（padloc）一致的移位信号（lvl_dn_int）的触发电平。

3. 发明申请

WO2010014443A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平输入/输出电路
公开(公告)号：WO2010014443A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/050978
申请日：2009-07-17
申请人： QUALCOMM INCORPORATED , SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： G01R19/165 , H03K19/0185 , H03K19/003
CPC分类号： H03K19/018507 , G01R19/16519 , G01R19/16552 , H03K19/00315
摘要： (213) has an input circui (M5,M6,M7) adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit (710) is coupled to the input circuit (M5,M6,M7) for latching a signal consistent with a detected level of an accepted signal.
摘要翻译：（213）具有适于接收用于检测特定电平的多个信号电平的信号的输入电路（M5，M6，M7）。信号电平包括第一信号电平和较大的第二信号电平。输入电路的电子元件具有小于第二信号电平的可靠性水平。锁存电路（710）耦合到输入电路（M5，M6，M7），用于锁存与所接收信号的检测电平一致的信号。

4. 发明申请

WO2015112483A1 SERIAL DATA TRANSMISSION FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) INTERFACES 审中-公开
标题翻译：用于动态随机存取存储器（DRAM）接口的串行数据传输
公开(公告)号：WO2015112483A1
公开(公告)日：2015-07-30
申请号：PCT/US2015/011998
申请日：2015-01-20
申请人： QUALCOMM INCORPORATED
发明人： SRINIVAS, Vaishnav , BRUNOLLI, Michael, Joseph , CHUN, Dexter, Tamio , WEST, David, Ian
IPC分类号： G06F13/16 , G06F13/42
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/4243 , G06F13/4295 , Y02D10/14 , Y02D10/151
摘要： Serial data transmission for dynamic random access memory (DRAM) interfaces is disclosed. Instead of the parallel data transmission that gives rise to skew concerns, exemplary aspects of the present disclosure transmit the bits of a word serially over a single lane of the bus. Because the bus is a high speed bus, even though the bits come in one after another (i.e., serially), the time between arrival of the first bit and arrival of the last bit of the word is still relatively short. Likewise, because the bits arrive serially, skew between bits becomes irrelevant. The bits are aggregated within a given amount of time and loaded into the memory array.
摘要翻译：公开了用于动态随机存取存储器（DRAM）接口的串行数据传输。代替引起偏斜关系的并行数据传输，本公开的示例性方面在总线的单个通道上串行地传送字的位。由于总线是高速总线，即使这些位一个接一个地（即，串行地）进入，第一位到达之间的时间和该字的最后一位的到达仍然相对较短。同样，由于这些位串行到达，所以位之间的偏移变得无关紧要。这些位在给定的时间内聚合并加载到存储器阵列中。

5. 发明申请

WO2015112326A1 PROVIDING MEMORY TRAINING OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) SYSTEMS USING PORT-TO-PORT LOOPBACKS, AND RELATED METHODS, SYSTEMS, AND APPARATUSES 审中-公开
标题翻译：使用端口到端口循环提供动态随机存取存储器（DRAM）系统的存储器训练以及相关方法，系统和装置
公开(公告)号：WO2015112326A1
公开(公告)日：2015-07-30
申请号：PCT/US2015/010218
申请日：2015-01-06
申请人： QUALCOMM INCORPORATED
发明人： SRINIVAS, Vaishnav , BRUNOLLI, Michael, Joseph , CHUN, Dexter, Tamio , WEST, David, Ian
IPC分类号： G11C29/02
CPC分类号： G11C7/1072 , G11C29/022 , G11C29/028
摘要： Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.
摘要翻译：提供使用端口到端口环回的动态随机存取存储器（DRAM）系统的存储器训练以及相关方法，系统和装置。在一个方面，DRAM系统中的第一端口经由环回连接耦合到第二端口。训练信号从片上系统（SoC）发送到第一个端口，并通过环回连接传递到第二个端口。然后训练信号返回到SoC，在那里可以通过SoC的闭环训练引擎检查训练信号。可以记录与硬件参数对应的训练结果，并且可以重复该过程，直到在闭环训练引擎上实现硬件参数的最佳结果。通过使用端口到端口环回配置，关于与DRAM系统相关联的定时，功率和其他参数的DRAM系统参数可以被更快地训练并且具有较低的启动存储器使用。

6. 发明申请

WO2014036456A2 METHOD AND APPARATUS FOR ROUTING DIE SIGNALS USING EXTERNAL INTERCONNECTS 审中-公开
标题翻译：使用外部互连路由DIE信号的方法和装置
公开(公告)号：WO2014036456A2
公开(公告)日：2014-03-06
申请号：PCT/US2013/057613
申请日：2013-08-30
申请人： QUALCOMM INCORPORATED
发明人： SRINIVAS, Vaishnav , YANG, Bernie, Jord , BRUNOLLI, Michael , WEST, David, Ian , PAYNTER, Charles, David
IPC分类号： H01L23/522 , H01L23/50 , H01L21/66 , H01L21/60 , H01L23/485
CPC分类号： H01L24/17 , H01L21/563 , H01L22/32 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/02377 , H01L2224/0401 , H01L2224/05558 , H01L2224/0556 , H01L2224/05569 , H01L2224/11462 , H01L2224/13028 , H01L2224/131 , H01L2224/13109 , H01L2224/13116 , H01L2224/13147 , H01L2224/14165 , H01L2224/16225 , H01L2224/16245 , H01L2224/27462 , H01L2224/29028 , H01L2224/29078 , H01L2224/29147 , H01L2224/3012 , H01L2224/3213 , H01L2224/73204 , H01L2224/81193 , H01L2224/81815 , H01L2224/831 , H01L2924/00014 , H01L2924/01322 , H01L2924/07802 , H01L2924/381 , H01L2924/0105 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.
摘要翻译：这里描述了使用外部互连在芯片的内部部分中布线管芯信号的方法的各个方面。该方法提供了耦合到管芯内部的电路的触点，其中触点暴露于管芯的外部部分。外部互连被配置为耦合这些触点，使得来自芯片内部部分的电路的信号可以被外部引导到管芯。在所公开的方法的各个方面，外部互连由模具的包装保护。

7. 发明申请

WO2017053097A1 MEMORY INTERFACE WITH ADJUSTABLE VOLTAGE AND TERMINATION AND METHODS OF USE 审中-公开
标题翻译：具有可调电压和终止的存储器接口及其使用方法
公开(公告)号：WO2017053097A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/051134
申请日：2016-09-09
申请人： QUALCOMM INCORPORATED
发明人： BRUNOLLI, Michael , THILENIUS, Stephen , ISAKANIAN, Patrick , SRINIVAS, Vaishnav
IPC分类号： G06F13/16 , G06F13/40 , G06F13/42 , G06F1/32 , H04L25/02
CPC分类号： G06F1/3275 , G06F1/32 , G06F1/3209 , G06F1/3287 , G06F1/3296 , G06F13/16 , G06F13/4086 , G06F13/4243 , G11C7/1072 , G11C11/4074 , H04L25/0278 , Y02D10/14 , Y02D10/172 , Y02D50/20
摘要： A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.
摘要翻译：存储器接口包括：上拉器件和下拉器件，其中所述上拉器件耦合在电源轨和数据线之间，并且其中所述下拉器件在所述数据线与地之间耦合; 以及电源，被配置为在终止的数据传输模式期间向电源轨提供第一电源电压，其中耦合到数据线的接收存储器接口具有有源的片上端接，并且其中电源还被配置为在片上终端不加载数据线的未终止数据传输模式期间，向第二电源电压提供第二电源电压，第二电源电压小于第一电源电压。

8. 发明申请

WO2017011351A1 LOW-POWER CLOCKING FOR A HIGH-SPEED MEMORY INTERFACE 审中-公开
标题翻译：用于高速存储器接口的低功耗时钟
公开(公告)号：WO2017011351A1
公开(公告)日：2017-01-19
申请号：PCT/US2016/041652
申请日：2016-07-08
申请人： QUALCOMM INCORPORATED
发明人： WEST, David , SRINIVAS, Vaishnav , BRUNOLLI, Michael , SUH, Jungwon
IPC分类号： G06F13/16
CPC分类号： G06F13/1689 , G06F13/4068 , G06F2213/0038 , G11C7/222 , H03L7/0807 , Y02D10/14 , Y02D10/151
摘要： Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command clock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.
摘要翻译：公开了在自适应通信接口中使用的方法，装置和系统。提供了一种自适应通信接口，其中在低功率操作模式中抑制了以高速操作模式提供的高速时钟。在低功耗工作模式下，低速命令时钟用于存储器件与片上系统，应用处理器或其他器件之间的数据传输。用于操作自适应通信接口的方法可以包括使用第一时钟信号来通过命令总线控制对存储器设备的命令的传输。在第一操作模式中，第一时钟信号控制通过自适应通信接口的数据传输。在第二种操作模式中，第二时钟信号通过自适应通信接口控制数据传输。第二时钟信号的频率可能大于第一时钟信号的频率。

9. 发明申请

WO2015105948A1 DYNAMIC RANDOM ACCESS MEMORY (DRAM) BACKCHANNEL COMMUNICATION SYSTEMS AND METHODS 审中-公开
标题翻译：动态随机存取存储器（DRAM）备用通信系统和方法
公开(公告)号：WO2015105948A1
公开(公告)日：2015-07-16
申请号：PCT/US2015/010583
申请日：2015-01-08
申请人： QUALCOMM INCORPORATED
发明人： WEST, David, Ian , BRUNOLLI, Michael, Joseph , CHUN, Dexter, Tamio , SRINIVAS, Vaishnav
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： G11C7/1063 , G06F11/1004 , G06F11/1048 , G06F12/00 , G11C11/406 , G11C11/40611 , G11C11/4076
摘要： Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.
摘要翻译：公开了动态随机存取存储器（DRAM）后向通道通信系统和方法。在一个方面，反向通道通信系统允许DRAM将错误校正信息和将警告信息刷新到片上系统（SoC），应用处理器（AP）或其他存储器控制器。

10. 发明申请

WO2010062834A1 LOW VOLTAGE DIFFERENTIAL SIGNALING DRIVER WITH PROGRAMMABLE ON-CHIP RESISTOR TERMINATION 审中-公开
标题翻译：具有可编程片上电阻终止的低电压差分信号驱动器
公开(公告)号：WO2010062834A1
公开(公告)日：2010-06-03
申请号：PCT/US2009/065314
申请日：2009-11-20
申请人： QUALCOMM INCORPORATED , DIXIT, Abhay S. , SRINIVAS, Vaishnav
发明人： DIXIT, Abhay S. , SRINIVAS, Vaishnav
IPC分类号： H03F3/45 , H04L25/02
CPC分类号： H03F3/45946 , H03F3/45179 , H03F3/45475 , H03F2200/78 , H03F2203/45424 , H03F2203/45434 , H03F2203/45641 , H03F2203/45642 , H03F2203/45646 , H03F2203/45681 , H03F2203/45682 , H03F2203/45686 , H03F2203/45696 , H03F2203/45702 , H03F2203/45726 , H04L25/0272
摘要： A low voltage differential signaling driver is disclosed and may include a current steering output circuit having a first driver output and a second driver output. The low voltage differential signaling driver may also include a programmable on-chip resistor.
摘要翻译：公开了一种低电压差分信号驱动器，并且可以包括具有第一驱动器输出和第二驱动器输出的电流转向输出电路。低电压差分信号驱动器还可以包括可编程片上电阻器。

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